esynr3z / axi_vip_demo

Xilinx AXI VIP example of use

https://positive-slack.github.io/blog/2021-04-24-xilinx-axi-verification-ip

axi fpga systemverilog xilinx

Xilinx AXI Verification IP (VIP) demo

AXI Slave verification example

Sources

src/axi_vip_master - AXI VIP Master - generated from Vivado -> IP Catalog -> AXI Verification IP
src/axi_ram - RAM with AXI Slave interface (from here)
src/xilinx_vip - from $XILINX_DIR/Vivado/2019.2/data/xilinx_vip directory
src/tb - testbench where all the components are instantinated

Simulation

Simulation in Vivado XSim can be started from sim folder. Scripts overview:

clean.sh - to remove all simulations artifacts
elab.sh - to elaborate all sources (Xilinx VIP is used as a library)
elab_nolib.sh - to elaborate all sources (Xilinx VIP sources are used - may be used as an example of how to run in other sim)
sim.sh - start simulation
run.sh - wrapper script; do elaboration and start simulation; optional argument nolib can be provided to choose the second elaboration script

Useful links

All those PDFs and ZIP can be also found in doc folder.

About

Xilinx AXI VIP example of use

https://positive-slack.github.io/blog/2021-04-24-xilinx-axi-verification-ip

axi fpga systemverilog xilinx

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