asic fpga eda registers register-descriptions systemrdl-compiler hardware-description-language command-line-tool amba apb axi csr systemverilog uvm uvm-register-model verilog

PeakRDL

PeakRDL is a free and open-source control & status register (CSR) generator toolchain. This project provides a command-line tool that unifies many aspects of register automation such as generating Verilog CSR RTL, compiling a C register abstraction layer, and many more. PeakRDL is centered around the SystemRDL register description language, but is also capable of working with other CSR specifications like IP-XACT.

This tool can:

Process SystemRDL 2.0 register descriptions.
Generate synthesizable SystemVerilog RTL register blocks.
Generate a C register abstraction header for software.
Import & export IP-XACT XML.
Create rich and dynamic HTML documentation.
Build a UVM register model abstraction layer.
... or extended this tool with your own plugins

Documentation

See the PeakRDL Documentation for more details.

About

Control and status register code generator toolchain

http://peakrdl.readthedocs.io

asic fpga eda registers register-descriptions systemrdl-compiler hardware-description-language command-line-tool amba apb axi csr systemverilog uvm uvm-register-model verilog

GNU General Public License v3.0

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