taichi-ishitani / tnoc

Network on Chip Implementation written in SytemVerilog

noc network-on-chip systemverilog amba amba-axi axi axi4 uvm

Network on Chip Implementation Written in SystemVerilog

Overview

This is a Network on Chip (NoC) Router/Fabric implementation written in SystemVerilog. It has following features.

2-D mesh network
Dimension order routing (X-Y routing)
Flow control
- Wormhole (FLIT based) flow control
- Virtual channel flow control
- On/Off Flow control
Configurable design
- Packet format
- Mesh size
- FIFO size
- etc.
Support standard bus protocol
- AMBA AXI4

Details

TBW

Contact

If you have any problems, questions, ideas, etc., you can post them on the following ways.

Copyright

Copyright (c) 2017-2018 Taichi Ishitani. See LICENSE for further details.

About

Network on Chip Implementation written in SytemVerilog

noc network-on-chip systemverilog amba amba-axi axi axi4 uvm

Apache License 2.0

Languages

Language:SystemVerilog 91.9%Language:Makefile 6.7%Language:Filebench WML 1.1%Language:Forth 0.2%Language:Shell 0.1%