efabless

There are 2 repositories under efabless topic.

edabk-hust / edabk_brain_soc
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
chatgpt chatgpt4 efabless openlane snn soc verilog
Language:Verilog 30
mattvenn / wrapped_project_template
Template project for the Zero to ASIC course group ASIC application
asic efabless google sky130 template
Language:Verilog 6
mattvenn / zero_to_asic_mpw6
MPW6 submission from the Zero to ASIC Course
asic efabless sky130 verilog mpw6
Language:Verilog 4
rejunity / zero-to-asic-wrapped-parallax
Tiny experimental ASIC design for efabless/OpenLane fab.
asic efabless openlane verilog fpga
Language:Verilog 4
saathi7 / Advanced-PD-using-OpenLANE-Sky130
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
efabless openlane sky130 vsd physical-design
4
fguzman82 / upb_natalius_soc
8 bit RISC Processor for SKY 130nm process
efabless processor-architecture risc sky130 verilog
Language:Verilog 1

edabk-hust / edabk_brain_soc