muhammadtalhasami-github-

There are 0 repository under muhammadtalhasami-github- topic.

muhammadtalhasami / Football_management_system
Football management system DBMS python GUI project repository
dbms dbms-project python pythongui mysql-database oracle-database muhammadtalhasami-github-dbms-python-gui-projects-muhammad-talha-sami-football-management-system football football-analytics football-data football-manager footballmanager football-management-system-project-football-management-system-projects-
Language:Python 4
muhammadtalhasami / RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
rv32i rv32i-processor pipeline-processor single-cycle-processor fetch-stage-pipeline muhammadtalhasami-github-risc-v-assembly risc-v-pipeline risc-v-processor hardware-designs system-verilog verilator verilog verilog-codes vhdl system-verilog-codes verilog-code-examples gtkwave risc-v-processor-images single-cycle-processor-gtkwave-image
Language:Verilog 2
muhammadtalhasami / muhammadtalhasami
muhammad-talha-muhammadtalhasami-github-muhhammad-talha-linkedin
0
muhammadtalhasami / openlane
This is my openlane repository in which we perform synthesis of our design/module.
cts-desgin-synthesis-floorplan-klayout muhammad-talha-github-muhammadtalhasami-github-netlist netlist-simulation-openlane openlane-flow openlane-github-openlanegithub-placement-rounting-synthesis
Language:Tcl 0
muhammadtalhasami / RTL_Practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
100daysofrtl hardware-coding muhammadtalhasami-github-rtl testbench verilog verilog-practice vhdl
Language:Verilog 0