muhammadtalhasami-github-

There are 1 repository under muhammadtalhasami-github- topic.

muhammadtalhasami / Football_management_system
Football management system DBMS python GUI project repository . This project is design on mysql database with python tiknter library for making a gui for the user
dbms dbms-project python pythongui mysql-database oracle-database muhammadtalhasami-github-dbms-python-gui-projects-muhammad-talha-sami-football-management-system football football-analytics football-data football-manager footballmanager football-management-system-project-football-management-system-projects-
Language:Python 8
muhammadtalhasami / muhammadtalhasami
My GitHub Profile README. Don't just fork, star it ⭐, so others can find it too! 🤝. Contributors are welcome.Feel free to contribute on my readme to make it more awesome 🔥🔥
awesome-github awesome-github-profiles awesome-github-repo awesome-readme github-profile github-profile-readme muhammad-talha-muhammadtalhasami-github-muhhammad-talha-linkedin
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muhammadtalhasami / RV32I_Single_Cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
rv32i rv32i-processor pipeline-processor single-cycle-processor fetch-stage-pipeline muhammadtalhasami-github-risc-v-assembly risc-v-pipeline risc-v-processor hardware-designs system-verilog verilator verilog verilog-codes vhdl system-verilog-codes verilog-code-examples gtkwave risc-v-processor-images single-cycle-processor-gtkwave-image
Language:Verilog 3
muhammadtalhasami / openlane
This is my openlane repository in which we perform synthesis of our design/module.
klayout muhammadtalhasami-github-netlist openlane openlane-flow synthesis cts-desgin-synthesis-floorplan-muhammad-talha-github-netlist-simulation-openlane-github-openlanegithub-placement-rounting-
Language:Tcl 1
muhammadtalhasami / RTL_Practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
muhammadtalhasami-github-rtl testbench verilog vhdl 100daysofrtl hardware-coding verilog-practice
Language:Verilog 1