rejunity / zero-to-asic-wrapped-parallax

Tiny experimental ASIC design for efabless/OpenLane fab.

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Parallax on ASIC

This is a small experimental ASIC project that renders procedural 2D scrolling terrain with stars using LFSRs and directly generates VGA 640x480@72Hz signal.

This experiment is a part of multi project submission to the Google/Efabless/Skywater shuttle.

The code is base upon the following FPGA examples:

Hopefully it looks something like this once ASIC has been taped out:

vga clock

License

This project is licensed under Apache 2

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Tiny experimental ASIC design for efabless/OpenLane fab.

License:Apache License 2.0


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