Nishit Bayen's repositories
100DaysOfRtlDesign
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
2_in_1_bot
A 2 in 1 robot able run on Bluetooth communication and able to avoid obstacle on it's own powered by "Vega processor" which is made in India indigenously by CDAC India
Enc_Dec_Xor
8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
sev_seg_FPGA
its a seven segment display controller in FPGA which counts in ascending order
Bin_2_BCD
Binary input BCD output in onboard 7-segment display of basys3
Binary_Input_FPGA
A Verilog code on Binary input and display output in 7 segment display in FPGA
Cisco_Projects
A simple office Networking demo has been implemented using Cisco Packet Tracer to understand the networking topologies and working of corporate networks between machine to machine.
Embedded_Systems_ST_Projects
"Exploring Creative Solutions with an Arduino Microcontroller: From Beginner to Advanced Projects"
eSim-Cloud
A web-based system for designing and simulating electronic (eSim) and Arduino circuits.
Full_adder-using-VHDL
Full adder program using VHDL language
GOOGLE_HOME_AUTOMATION
By this code you can control your home appliences by a nodemcu :
Internet-of-Things-with-ESP32
Developing IoT Projects with ESP32, published by Packt
Learn-FPGA-Programming
Learn FPGA Programming, published by Packt
Modern-Computer-Architecture-and-Organization-Second-Edition
Modern Computer Architecture and Organization – Second Edition, Published by Packt
nishit0072e
Config files for my GitHub profile.
Register_PIPO_PISO
Parallel in Parallel out, Parallel in Serial out Register Implementation with expansion Capabilities
roboschool
DEPRECATED: Open-source software for robot simulation, integrated with OpenAI Gym.
RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
sev_seg_rev_FPGA
A VERILOG code on seven segment display controller which counts in descending order
T_FlipFlop-using-VHDL
T FlipFlop is created with frequency divider in basys3 FPGA board of family Artix-7 with VHDL language
TCP-Calculator
A local server based TCP Calculator
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
VLSI-Fundamentals-A-Practical-Approach-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor