Angelo Jacobo (AngeloJacobo)

AngeloJacobo

Geek Repo

Location:Bulacan, Philippines

Home Page:https://www.linkedin.com/in/angelo-jacobo

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Angelo Jacobo's repositories

UberDDR3

Open-sourced DDR3 controller

Language:VerilogLicense:GPL-3.0Stargazers:87Issues:6Issues:0

FPGA_Book_Experiments

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

Language:VerilogLicense:MITStargazers:76Issues:5Issues:0

RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Language:VerilogLicense:MITStargazers:47Issues:4Issues:1

FPGA_OV7670_Camera_Interface

Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps

Language:VerilogLicense:MITStargazers:46Issues:5Issues:0

FPGA_RealTime_and_Static_Sobel_Edge_Detection

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Language:VerilogLicense:MITStargazers:37Issues:2Issues:2

OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

License:MITStargazers:37Issues:2Issues:0

FPGA_SDRAM_Controller

SDRAM controller optimized to a memory bandwidth of 316MB/s

Language:VerilogLicense:MITStargazers:22Issues:3Issues:0

DDR3-Notes

My notes for DDR3 SDRAM controller

License:MITStargazers:19Issues:3Issues:0

ULX3S_FPGA_Camera_Streaming

Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board

Language:VerilogLicense:MITStargazers:16Issues:4Issues:1

ULX3S_FPGA_Sobel_Edge_Detection_OV7670

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

Language:VerilogLicense:MITStargazers:14Issues:2Issues:0

FPGA_Asynchronous_FIFO

FIFO implementation with different clock domains for read and write.

Language:VerilogLicense:MITStargazers:12Issues:2Issues:0

FPGA_I2C_Implementation

Bit-bang i2c protocol for interfacing with DS1307 RTC

Language:VerilogLicense:MITStargazers:7Issues:2Issues:0

Customize-Android-Apps

This contains my notes on how to customize existing Android apps such as changing app name, app icon, hiding app from the app drawer, and others.

License:MITStargazers:4Issues:2Issues:0

ddr3-controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

Language:VerilogStargazers:1Issues:1Issues:0

icestudio-examples

:snowflake: Icestudio examples - Community contributions

Language:Rich Text FormatLicense:GPL-3.0Stargazers:1Issues:1Issues:0

Python_Scripts

Just a collection of my python scripts

Language:PythonLicense:MITStargazers:1Issues:2Issues:0

SDCard_Driver_Test

Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.

Language:VerilogLicense:MITStargazers:1Issues:2Issues:0

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:0

AngeloJacobo

Config files for my GitHub profile.

Stargazers:0Issues:2Issues:0

DDR

A simple DDR3 memory controller

Language:VerilogLicense:GPL-3.0Stargazers:0Issues:1Issues:0

eth10g

10Gb Ethernet Switch

Language:CLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:CLicense:MITStargazers:0Issues:1Issues:0

rtl

temporary repo

Language:C++Stargazers:0Issues:2Issues:0

zipstormmx

ZipSTORM-MX, an iCE40 ZipCPU demonstration project

Language:VerilogStargazers:0Issues:1Issues:0