Del Hatch (delhatch)

delhatch

Geek Repo

Location:Seattle, WA

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Del Hatch's repositories

PiPod_ePaper

PiPod MP3 player with a 250 × 122 e-Paper screen

Spectrum

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

Language:VHDLStargazers:29Issues:5Issues:0

Zynq_UDP

Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.

ESP32_to_SMA

ESP32 connects to SMA Sunny Boy inverter over Bluetooth

VGA_mem_mapped

Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.

Language:VHDLStargazers:15Issues:2Issues:0

Red_Tracker

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

Language:VerilogStargazers:14Issues:3Issues:0

Zedboard_Mandel

Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.

Language:VHDLStargazers:8Issues:1Issues:0

IIR_EQ

IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.

Language:VHDLStargazers:6Issues:1Issues:0

Pure_Mandel

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

Language:VerilogStargazers:6Issues:2Issues:0

PiPod_Zero2W

Modifying the PiPod project for the Pi Zero 2 W.

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falling-time-clock

A clock that displays the numbers as physical falling numbers.

Language:ProcessingStargazers:2Issues:3Issues:1

Multi_IIR

Multi-band IIR filter in Verilog. Uses time-domain multiplexing of a single, fixed-point, IIR filter to create a 27-band filter.

Language:VHDLStargazers:2Issues:1Issues:0

arduino-esp32

Arduino core for the ESP32

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DES_decrypt

C code DES decryption. Takes an encrypted file along with a file containing a DES key, and outputs the plaintext file.

Language:C++Stargazers:1Issues:1Issues:0

Flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

Language:VerilogStargazers:1Issues:1Issues:0

Mandel_HLS

Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.

Language:VHDLStargazers:1Issues:1Issues:0

zedboard_ethernet_io_ctrl

Control the IO on the PMOD's on the Zedboard via the Ethernet port using baremetal and LWIP

Language:CStargazers:1Issues:1Issues:0

ESP32_to_Primex

For a Primex transmitter, uses an ESP32 to simulate the GPS receiver. Connects to NTP to get the time.

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oot

Gnuradio OOT custom modules

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PiPod

From PiPod_Zero2W -- w/ major overhaul of the GUI functions to operate more like the Sony NWZ-A17 media player.

Language:PythonLicense:MITStargazers:0Issues:1Issues:0