There are 3 repositories under synopsys topic.
This is a tutorial on standard digital design flow
embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC
Customized UVM Report Server
:book: Mastering FPGASIC Book
A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
:star2: Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
Example of a full DC synthesis script for a simple design
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.
Master degree project for Synthesis and Optimization of Digital Systems
iDoka's web page on Github
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
A small collection of tutorials and tools for ASIC design.
Command completion for Synopsys (Black Duck) Detect commands
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
Waveform viewer for Synopsys CustomCompiler, text table format, simulation data
Implementation of a MIPS CPU using Verilog.
2AMD15 - Big Data Management - Prof. Papapetrou - TU/e
Designing a Pseudo dynamic latched comparator in 28nm CMOS Technology using Synopsys Tools.
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.
Mold: A Modern Linker 🦠 ARCV2 Support, Linker Script support is the aim for embedded projects
Ansible Role: Polaris - Installs and configures Polaris CLI
2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology