de2-115
There are 6 repositories under de2-115 topic.
delhatch / Spectrum
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
Language:VHDL 29Goshik92 / FFTVisualizer
This project demonstrates DSP capabilities of Terasic DE2-115
Language:Verilog 25Matrix multiplication on multiple Nios II cores
Language:C 15Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)
Language:Verilog 14ChienKaiMa / HDR-Imaging-with-FPGA
High Dynamic Range imaging with Altera DE2-115.
Language:SystemVerilog 11FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.
Language:Verilog 6snwjas / DE2-Electric-Timer
DE2简易电子计时器，使用VHDL语言开发，在DE2-115开发板上测试运行通过。该电子计时器具有四种工作模式：正常计时、从外部设置当前的小时数、从外部设置当前的分钟数、从外部设置当前的秒数，同时具有可逆的计时功能。
Language:VHDL 6- Language:Verilog 5
Дипломная работа специалиста за 2015 год на тему "Акустическая система мониторинга на основе пространственной фильтрации звуковых сигналов".
Language:TeX 4- de2115-simple-mips-without-pipeline
mateuspinto / de2115-simple-mips-without-pipeline
A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.
Language:SystemVerilog 4 - Language:VHDL 4
fbponz / Terasic-DE2-115-NiosII-uCosII
Design for board DE2-115, microprocessor soft running a uCOS-II(Real Time Operating System). Application to test is a Lift program
Language:Verilog 3SamanKhamesian / Special-Purpose-Processor
This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)
Language:Verilog 3- Language:Verilog 2
- Language:Verilog 2
- Language:VHDL 1
Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).
Language:Verilog 1- Language:Verilog 1
jpenolio75 / smp8
An implementation of a simple 8-bit microprocessor on an Altera DE2-115 board for UNLV CpE 300L Digital Systems Architecture and Design final project.
Language:Verilog 1An implementation of the popular Tron arcade game on the Altera DE2-115 board for UNLV CpE 302 Synthesis and Verification Using Programmable Devices final.
Language:SystemVerilog 1junzhengca / space-enemies
Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.
Language:Verilog 1jvmcarneiro / de2-115-virtual-input
Virtual GUI for controlling the Altera DE2-115 board.
Language:Python 1- Language:Verilog 1
- Language:Tcl 1
- Language:VHDL 1
LegendaryPredz / FPGA-CPU
A simple CPU created in Quartus Prime using VHDL for the DE2-115 FPGA Development Board.
Language:VHDL 0LukasJanavicius / DE2-115-USB-DEVICE-example-
Patched Altera USB DEVICE example with windows 10 drivers
Language:Verilog 0- Language:C 0
egk696 / GraphicsController
Development of an FPGA-based graphics controller
Language:VHDLHuIsJason / J.O.S.H.-Jump
A platformer game based on Gravity Guy, using a DE2 hardware board
Language:VerilogOrthodoxCaveDweller / FPGiAno-Tiles
Short description of this repository http://www.speedrunners.nl
Language:C
