hukenovs

Alexander Kapitanov's repositories

dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Language:Jupyter NotebookGPL-3.0912 60 6

hagrid

HAnd Gesture Recognition Image Dataset

Language:Python476 12 47

coursera_ml_da_specialization

Coursera Specialization: Machine Learning and Data Analysis (Yandex & MIPT)

Language:Jupyter Notebook164 50

easyportrait

EasyPortrait - Face Parsing and Portrait Segmentation Dataset

Language:Python160 6 18

chaospy

Chaotic attractors with python (Lorenz, Rossler, Rikitake etc.)

Language:PythonGPL-3.089 7 1

intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Language:VHDLGPL-3.072 7 1

hh_research

Автоматизация поиска и исследования вакансий с сайта hh.ru (Headhunter) с помощью методов Python. Классификация данных, поиск статистических параметров.

Language:Jupyter NotebookGPL-3.068 9 3

slovo

Slovo: Russian Sign Language Dataset and Models

Language:Python55 50

fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Language:VHDLGPL-3.048 8 1

tcl_for_fpga

TCL scripts for FPGA (Xilinx)

Language:TclMIT28 40

github_backup

GitHub saver for stargazers, forks, repos

Language:PythonMIT25 20

math

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Language:MATLABGPL-3.024 5 1

dsppy

Python Digital signal processing (DSP) modules

Language:Python18 3 1

adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

Language:VHDLMIT11 30

fp23_logic

Floating point FP23 core on VHDL. For Xilinx FPGAs. Include base converters and some math functions.

Language:VHDLMIT10 50

blackman_harris_win

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

Language:VHDLGPL-3.08 20