iDoka

awesome-canbus

:articulated_lorry: Awesome CAN bus tools, hardware and resources for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.

awesome-embedded-software

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

awesome-automotive-can-id

:tractor: Collect of CAN IDs and its payloads for various car brands/models in one place. Might be useful for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.

awesome-linbus

:articulated_lorry: An awesome LIN bus tools, hardware and resources. It helps a reverse engineering LIN bus devices with lightly specializing in automotive embedded controller software and communication understanding.

awesome-fpga-boards

:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

eda-scripts

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

mastering-fpgasic-book

:book: Mastering FPGASIC Book

GOST-28147-89

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

raspberrypi-recipes

Collection of practice recipes for RPi

hdl-secded-producer

MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.

dotfiles

.files from my homebrewed CentOS 7 | Ubuntu 18.04

awesome-nRF5

nRF5xxxx family

awesome-stm8

STM8 awesome list

hdl-stuff

HDL things for FPGA and ASIC

SmartRC-CC1101-Driver-Lib

This driver library can be used for many libraries that use a simple RF ASK module, with the advantages of the cc1101 module. It offers many direct setting options as in SmartRF Studio and calculates settings such as MHz directly.

volvo-p3-knowledge-base

My knowledge base for Volvo Platform 3 models (XC60, XC70, V70, S60, V60, S80)

HDL-Coding-Style-Standards

Collection of Coding Style Standards for Verilog and VHDL

iDoka

Config files for my GitHub profile

platform-openhw

OpenHW Group: development platform for PlatformIO

russian-semiconductor-companies

List of Semiconductor companies in Russia

asciidoc-table-beautifier

This repository contains a script that visually formats simple tables in asciidoc files into a more readable format.

corsair

Control and Status Register map generator for HDL projects

hdlparse

Simple Python parser for extracting HDL (VHDL or Verilog) documentation

mch2022-badge-hardware

statistics-acquisition-module

Statistics Acquisition Module on Verilog

wavedrompy

WaveDrom compatible python command line

.github

Default files for all repositories in the iDoka's account on GitHub

symbolator

Generate symbols from HDL components/modules

verilog-cleaner

A GitHub Action for linting and formatting Verilog code

WD-My-Book-Live-retrofitting

Retrofitting NAS My Book Live from WD