sdram-controller

There are 0 repository under sdram-controller topic.

• PrimeMHD / FPGA_ThreeLevelStorage

  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

  fpgaverilogddrsd-cardsdram-controller
  Language:Coq 118

• ultraembedded / core_sdram_axi4

  SDRAM controller with AXI4 interface

  verilogaxi4sdram-controllerfpga
  Language:C++ 98

• yigitbektasgursoy / SDRAM_Verilog

  Verilog HDL implementation of SDRAM controller and SDRAM model

  sdramsdram-controllerverilogverilog-hdlverilog-projectvivado
  Language:Verilog 32

• AngeloJacobo / FPGA_SDRAM_Controller

  SDRAM controller optimized to a memory bandwidth of 316MB/s

  fpgasdramverilogsdram-controller
  Language:Verilog 28

• Arkowski24 / sdram-controller

  Simple SDRAM Controller for DE10-Lite.

  fpgasdramsdram-controllerverilog
  Language:Verilog 13

• MinatsuT / CYC1000_SDRAM

  A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

  fpgacyclone-10lpcyc1000sdramquartus-primesdram-controllernios2
  Language:Verilog 13

• cw1997 / SDRAM-Controller

  SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

  sdramsdram-controllerverilog-projectsystemveriloghardwarehardware-designs
  Language:HTML 12

• jakubcabal / sdram-tester-fpga

  SDRAM Tester implemented in FPGA

  fpgasdramcyc1000sdram-controllerpythonmeasures-throughputsdram-testervhdl
  Language:VHDL 10

• egk696 / EDAC_SDRAM_Controller

  Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

  cots-sdramembedded-systemsfault-tolerantfpgaquartus-primesdramsdram-controllervhdlvivado
  Language:Verilog 9

• agg23 / sdram-controller

  A HDL SDRAM controller designed for retro hardware and FPGAs

  analogue-pocketfpgamisterfpgasdramsdram-controller
  Language:SystemVerilog 8

• ShwetaKiranTotla / Micro-processor-Design-Verification

  Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

  cocotbcocotb-testingdesign-verificationflashmakefilepythonriscsdramsdram-controllertestbenchuartverification
  Language:Verilog 6

• armleo / sdram_controller

  SDR SDRAM Controller with Avalon-MM bus

  sdramverilogfpgasdram-controller
  Language:Verilog 3

• kevin861222 / SDRAM_controller

  SDRAM controller

  digital-ic-designsdram-controller
  Language:Verilog 3

• oskarwires / sdram_controller

  High-Speed SystemVerilog SDRAM Controller

  sdramsdram-controllerfpga
  Language:SystemVerilog 3

• yasnakateb / SdramController

  🛠 A SDRAM controller in Verilog HDL

  sdramsdram-controllerverilogverilog-hdlicarus-verilogiverilogmemory-controller
  Language:Verilog 3

• teekamkhandelwal / SRAM_Controller

  The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

  memorymemory-controllerquestasimsramsram-controllerverilogverilog-projectvivadovlsi-designsram-controller-advancedsram-features-power-security-brustmemory-managementverlog-hdlsdramsdram-controllerenhanched-sram-controller
  Language:Verilog 2
• SDRAM-Controller-Design

  Nikhil-Ashok-Kumbhar / SDRAM-Controller-Design

  Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required

  sdram-controller
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