adibis

DDR2_Controller

DDR2 memory controller written in Verilog

nvim

NeoVim configuration files

Interrupt_Controller

An 8 input interrupt controller written in Verilog.

uvmBasics

Basics of UVM via an APB slave

alu_tb

Basic ALU testbench written in UVM for experiments

.vim

Vim configuration directory

ATPG

Brute force ATPG -- school project

beagleBoneBlack

BeagleBone Black projects

mips_5stage

Very basic 5 stage MIPS pipelined processor core.

nurikabe

Web based nurikabe implementation. Responsive design, intended for mobile use.

uvm_agents

UVM agents

aoc_2018

Advent of code 2018

bullsandcows

Minimal Bulls and Cows written in JS. Intended for mobile usage.

crawl

Dungeon Crawl: Stone Soup official repository

eepromprogrammer

etc

My configuration files

jekyllNerditya

Code for nerditya.com on Jekyll

nanocNerditya

Nanoc blog hosted on nerditya.com

neovim

Vim-fork focused on extensibility and agility.

nvim_lsp

Neovim config in LSP

vim-SystemVerilog

SystemVerilog syntax highlight/indent support in vim

vimBook