Nidhinchandran47

Nidhin Chandran's repositories

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language:Verilog10 1 1

implementation of a 5 port router

Language:Verilog500

This is the VHDL code for a floating point adder

Language:VHDL2 10

This is a 4 bit MAC unit ,which is the basic unit of matric multiplier used in TPU

Language:VHDL200

This is the verilog code for a 4bit arithmetic and logic unit which can do 8 operations

Language:Verilog1 10

Config files for my GitHub profile.

miniproject done at nielit calicut while a workshop on fpga architecture

Language:Verilog1 10

ARAS-AUTOMATIC REMOTE AQUAPONIC SYSTEMS

Language:C++010

This is a high-efficiency boost converter designed for quicker charging of electric vehicles.Prototype 1.

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Markdown Cheatsheet for Github Readme.md

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Verilog implementation of a mips32 processor

Language:Verilog010

A MIPS based microprocessor and a python script for automatic generation of testbench corresponding to the input assembly file

Language:Verilog000