Mihir Rajendra Mahajan's repositories
VerilogHDL-Codes
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
Perl_Scripts
Perl scripts to automate in verilog testbench
Python-and-Machine-Learning
Python and Machine Learning Source Code
Arduino_geek_projects
Arduino Projects
Color_Classification_Python_OpenCV_Machine_Learning
Color Classification using Python, OpenCV, and Machine Learning
LabVIEW-Applicaiton-snapshots
Snapshots of LabVIEW applications, GUI of Utilities and ATEs