mongrelgem

Krishna Subramanian's repositories

Implementing Different Adder Structures in Verilog

Language:VerilogApache-2.049 20

Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment

Apache-2.01000

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

Language:VHDL9 20

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language:VerilogApache-2.05 10

Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2

Language:PerlApache-2.04 20

A Recurrent Sequence to Sequence, multi-domain generative conversational model chatbot implemented in pytorch

Language:PythonApache-2.0200

Modular Verilog I2C Interface Components for Rapid Prototyping in FPGAs with MyHDL Testbench

Apache-2.0000