flasonil

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Arm Ltd

Cambridge

linkedin.com/in/ilario-coppola-2b8a42139

Ilario Coppola's repositories

Deep-Neural-Network-for-CS-based-signal-reconstruction-on-STM32-MCU-board

Compressed Sensing signal decoding with DNN oracle on STM32

Language:PythonMIT16 10

Serial-Multiplier

16 bit serial multiplier in SystemVerilog

Language:SystemVerilog1201

APB_PWM

Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

Language:SystemVerilog8 10

riscv

Language:SystemVerilogNOASSERTION2 20

CMOS_2stage_op-amp_design

Language:SourcePawn100

countdown_circuit

Language:SystemVerilog100

intel8085

Language:SystemVerilog100

lockstep_unit

Language:SystemVerilog1 10

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

Language:SystemVerilogNOASSERTION100

pulp_cluster

Language:SystemVerilogNOASSERTION1 10

pulp_soc

Language:SystemVerilogNOASSERTION100

ripple_carry_adder

Language:SystemVerilog100

shift_register

Language:SystemVerilog100

single_cycle_MIPS

100

pulp-nn

Language:CApache-2.0000

Simple-Compass-on-ST-board

Coded on STM32F401C-discovery

Language:CMIT000