zcu102
There are 1 repository under zcu102 topic.
Xilinx / Vitis-Tutorials
Vitis In-Depth Tutorials
Language:C 1283li3tuo4 / rc-fpga-zcu
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Language:Tcl 58- Language:C 36
LaErre9 / Zynq_Ultrascale_Vitis_AI_CNN_ZCU102
Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.
Language:Jupyter Notebook 15jdibenes / zcu102_two_cameras
ZCU102 two IMX274 camera design.
Language:Tcl 9gpanders / zynqmp-boot-apps
Generate and install boot apps for the Zynq MPSoC device
Language:Makefile 6Collection of FPGA modules for video capture and processing.
Language:Tcl 4jracevedob / MPSoC_Networking
This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)
Language:VHDL 3giuseppericcio / Zynq_Ultrascale_Vitis_AI_CNN_ZCU102
Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.
Language:Jupyter Notebook 1BlaCkinkGJ / Flash-Board-Tester
:white_check_mark: The testing program validates the BlueDBM flashboard for the ZCU102 motherboard.
Language:C 0edowson / Vitis_Embedded_Platform_Source
Xilinx Vitis repository containing video streaming and machine learning reference designs.
Language:CThis directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.
