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litex

Build your hardware, easily!

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litepcie

Small footprint and configurable PCIe core

Language:PythonNOASSERTION465 28 68

litedram

Small footprint and configurable DRAM core

Language:PythonNOASSERTION371 24 163

liteeth

Small footprint and configurable Ethernet core

Language:PythonNOASSERTION207 17 65

litescope

Small footprint and configurable embedded FPGA logic analyzer

Language:PythonNOASSERTION166 16 22

pcie_screamer

PCIe Screamer - TLPs experiments...

Language:CBSD-2-Clause163 18 10

litesata

Small footprint and configurable SATA core

Language:PythonNOASSERTION123 18 17

litesdcard

Small footprint and configurable SDCard core

Language:PythonNOASSERTION107 13 12

colorlite

Take control of your Colorlight FPGA board with LiteX/LiteEth :)

Language:PythonBSD-2-Clause94 10 8

litex-acorn-baseboard

LiteX development baseboards arround the SQRL Acorn.

Language:PythonNOASSERTION56 15 10

liteiclink

Small footprint and configurable Inter-Chip communication cores

Language:PythonNOASSERTION53 11 10

litex_m2sdr

LiteX based M2 SDR FPGA board.

Language:CBSD-2-Clause5300

litejesd204b

Small footprint and configurable JESD204B core

Language:PythonNOASSERTION39 4 4

litex_rp2040_pmod_test

Test of a RP2040 PMOD attached to a LiteX SoC.

Language:Python23 4 1

xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing

Language:CBSD-2-Clause23 7 13

thunderscope

LiteX based FPGA gateware for Thunderscope.

Language:Python19 7 12

litex_verilog_axi_test

Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.

Language:Python14 5 2

litex_hw_ci

LiteX Hardware CI tests.

Language:Python8 4 16

openFPGALoader

Universal utility for programming FPGA

Language:C++Apache-2.05 10

litepcie_ptm_test

LitePCIe PTM support / test repo.

Language:Python4 6 11

vhdl2doc

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litex_openwrt_test

Test of OpenWRT on LiteX SoCs.

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CTU-CAN-FD

This is a mirror repository for official CTU CAN FD repository:

NOASSERTION100

litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.

Language:Verilog1 3 9

openocd

Spen's Official OpenOCD Mirror (no pull requests)

Language:CGPL-2.01 20

FASTSCOPE

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LimeSDR-XTRX_LiteX_GW

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litex_64bit_addressing_test

Test/PoC of 64-bit addressing in LiteX.

Language:Python03 4

litex_xtrx

XTRX LiteX/LitePCIe based alternative Gateware/Software.

Language:C++BSD-2-Clause000

openfpga-pong

FPGA Pong implementation, specifically for the Analogue Pocket

Language:VerilogMIT010