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5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals are emulated. Support running mainline Linux. 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设,并支持运行主线Linux。
RISC-V 64 CPU