aignacio

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

mpsoc_example

nox

RISC-V Nox core

axi_dma

General Purpose AXI Direct Memory Access

cocotbext-ahb

Cocotb AHB Extension - AHB VIP

nox_freertos

cdc_components

Collection of different designs for clock domain crossing

soc_components

deca_board_demo

async_gp_fifo

blinky

Example LED blinking project for your FPGA dev board of choice

bus_arch_sv_pkg

AMBA SystemVerilog structs

ethernet_axi

AXI wrapper around Ethernet module

fusesoc-cores

FuseSoC standard core library

riscv-arch-test-nox

riscv-formal

RISC-V Formal Verification Framework

verilog-ethernet

Verilog Ethernet components for FPGA implementation

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

aignacio.github.io

chisel-template

Chisel HDL Template Repository

cocotb_design_playground

Template repository for Cocotb RTL development

docker-cronicle

Simple, lightweight, beautiful webui Cronjob / Scheduled task docker solution.

ipsocgen_template

openmp_eval_arm

pcie_example

pp-sp-reference-design

rr_arbiter

rtl_dev_container

Github Actions Container for RTL development

todeletelater

verilog-axi

Verilog AXI components for FPGA implementation