nexys4

There are 0 repository under nexys4 topic.

Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition
车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
cv fpga-cortex-m3 vivado arm nexys4
Language:VHDL 114
rossmacarthur / mawg
Modulation and Arbitrary Waveform Generator
fpga verilog nexys4
Language:Verilog 13
ilyajob05 / verilog_modules
verilog modules
verilog rmii i2c spi uart usart timer memory 7-segment synchronization pll nexys4 nexys-4-spartan-3e nexys4-board fpga xilinx xilinx-fpga
Language:Verilog 11
yuanbo-peng / Combination-Lock
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
vhdl digital-design combination-lock debounce-button finite-state-machine multi-digits-display random-numbers nexys4 vivado
Language:VHDL 6
maxislash / MazeGame
Realization of a maze game on FPGA using VHDL
fpga maze nexys4 vhdl xilinx
Language:VHDL 3
homerflander / One-Time-Pad-FPGA
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
otp verilog vivado one-time-pad diligent seven-segment nexys4
Language:Verilog 1
ilyajob05 / verilog_SPI
SPI module for Nexys 4 Artix-7 FPGA Trainer Board
spi verilog artix-7 nexys4 nexys4-board nexys-4-spartan-3e fpga fpga-programming xilinx xilinx-fpga
Language:Verilog 1
LCSR-lab / NetFi3
NetFI-3: Netlist Fault Injection system - Version 3
verilog vhdl fault-injection nexys4 netlist vivado thesis engineering computer-science computer-engineering
Language:TeX 1
maxislash / 8BitProc
Implementation of an 8-bit processor on a Xilinx FPGA in VHDL
fpga nexys4 processor processor-architecture vhdl xilinx
Language:VHDL 1
pedrovt / cr-square-root-cop
A FPGA Based Square Root Approximation Coprocessor
fpga vhdl fpga-soc fpga-accelerator square-root xilinx nexys4
Language:VHDL 1
smdsbz / ElevatorController
Digital Logic curriculum design - FPGA-based elevator controller
fpga nexys4 verilog digital-logic
Language:C 1
LowPassFilterFPGA
splAcharya / LowPassFilterFPGA
Designed and Implemented a low pass filter in Nexys 4 FPGA
nexys4 fpga matlab filter-design simulink lowpass-filter digital-signal-processing dsp xilinx-fpga xilinx-vivado
Language:VHDL 1
alejandromdnsls / ESCOMips
mips-architecture microprocessor vhdl-code nexys4
Language:C 0
damienen / ADXL362_Nexys4
This repository contains a simple accelerometer controller for the Nexys 4 board
vhdl nexys4 fpga
Language:VHDL 0
fpgaedu / ci
Continuous integration environments for FPGAedu projects
vivado linux digilent nexys4 vagrant continuous-integration
Language:Ruby 0
jens-j / mandelbrot
Real-time FPGA mandelbrot explorer with SNES controller and VGA output
vhdl visualization nexys4 snes vga real-time video fpga
Language:VHDL 0
JochiSt / Nexys4-liteeth
use the liteeth core on the Nexys4 board without SoC
hdlmake liteeth nexys4 vhdl
Language:Tcl

nexys4

Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition

rossmacarthur / mawg

ilyajob05 / verilog_modules

yuanbo-peng / Combination-Lock

maxislash / MazeGame

homerflander / One-Time-Pad-FPGA

ilyajob05 / verilog_SPI

LCSR-lab / NetFi3

maxislash / 8BitProc

pedrovt / cr-square-root-cop

smdsbz / ElevatorController

splAcharya / LowPassFilterFPGA

alejandromdnsls / ESCOMips

damienen / ADXL362_Nexys4

fpgaedu / ci

jens-j / mandelbrot

JochiSt / Nexys4-liteeth