nexys-a7

There are 1 repository under nexys-a7 topic.

tomas-fryza / vhdl-course
VHDL course at Brno University of Technology
brno-university-of-technology fpga vivado nexys-a7 vhdl teroshdl
Language:Tcl 77
sifferman / fusesoc_template
Example of how to get started with olofk/fusesoc.
fusesoc tinyfpga-bx nexys-a7 icarus-verilog vivado yosys nextpnr-ice40 icestorm
Language:Python 12
Lombiq / Hastlayer-Hardware-Framework---Xilinx
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.
fpga xilinx nexys-4 nexys-a7
Language:VHDL 5
einstein07 / Yoda
(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.
fpga-programming nexys-a7
Language:VHDL 2
GeorgeDong32 / FIADS
An FPGA-based image acquisition and display system, referred to as FIADS.
fpga nexys-a7 ov7670 verilog
Language:Verilog 2
matthew-william-lock / Image-Masking-Accelerator
This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.
fpga image-masking nexys-a7 hardware-acceleration
Language:VHDL 2
amsacks / OV7670-Video-Processing
Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board
fifo handshake-protocol nexys-a7 ov7670 pipeline sobel-edge-detector systemverilog verilog
Language:Verilog 1
zexsoft / NexysLib
Nexys A7 drivers for RISC-V
risc-v nexys-a7 drivers fpga
Language:C 1
ADolbyB / vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Language:VHDL 0
Akshaya114 / T20-Cricket-Game
T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.
cricket cricket-game fpga-projects ipl nexys-a7 simulation
Language:Verilog 0
Choijh03 / FPGA_NEXYS_A7_PROJECTS
fpga nexys-a7 verilog
Language:Verilog 0
jswenke / pong
nexys-a7 pong-game vga-driver vhdl vhdl-examples
Language:SystemVerilog 0
R4sp1 / digital-electronics-1-project
Team project in BPC-DE1 course on FEEC BUT
brno-university-of-technology fpga nexys-a7 uart vhdl vivado
Language:VHDL 0
tristynferreiro / ISD-PO
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
fpga-accelerator nexys-a7 steganography
Language:VHDL 0
xshele01 / Digital-electronics-1
Digital Electronics 1 course at Brno University of Technology
vhdl vivado fpga nexys-a7 vutbr brno-university-of-technology
Language:VHDL 0
Joel-Dandin / vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
boom fpga linux genesys2 nexys nexys-a7 nexys-video risc-v riscv riscv64 rocketchip vc707 kc705
Language:Tcl
KOTerra / Digital-VHDL-Locker
A digital locker made for Nexys A7 using Xilinx Vivado and VHSIC Hardware Description Language
nexys-a7 vhdl vivado
Language:Tcl

nexys-a7

tomas-fryza / vhdl-course

sifferman / fusesoc_template

Lombiq / Hastlayer-Hardware-Framework---Xilinx

einstein07 / Yoda

GeorgeDong32 / FIADS

matthew-william-lock / Image-Masking-Accelerator

amsacks / OV7670-Video-Processing

zexsoft / NexysLib

ADolbyB / vhdl-fpga-nexys-a7

Akshaya114 / T20-Cricket-Game

Choijh03 / FPGA_NEXYS_A7_PROJECTS

jswenke / pong

R4sp1 / digital-electronics-1-project

tristynferreiro / ISD-PO

xshele01 / Digital-electronics-1

Joel-Dandin / vivado-risc-v

KOTerra / Digital-VHDL-Locker