Yiğit Süoğlu's repositories
Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
Carry-Save-Multiplier
Parameterized and 4-bit carry save multiplier design
IR-Transreceiver
Encoder and decoder modules for infrared receivers, transmitters and remotes
Digital_Clock
Verilog code for a digital clock
Queue-Management-System
Simple queue management system
Verilog-Utilty-Modules
Collection of utility modules written in Verilog
VSC-Snippets
Some snippets for Verilog HDL to be used in VS Code
xorshiftPlus
Pseudorandom number generator
Sequential-CRC-Generator
Pair of modules to calculate crc values sequentially
Simple-UART
Set of simple modules to communicate via UART
AXI-GPIO
Custom AXI GPIO core with up to 32 input and 32 output ports
AXI-lite-slave
Slaves for AXI-lite interface
AXIS-Buffer
AXIS buffer to keep data until next stage accepts it. Does not add any latency.
AXIS-Split
Splits one AXI-Stream transmission to two.
Bash-Scripts
Repository for my bash scripts
Image-to-Binary
Simple script to convert images to BMP files or raw RGB binary file.
MCP9808
Simple interface for MCP9808 temperature sensor
Rust-Exercises
Collection of exercises to learn rust
Simple-I2C
Set of simple modules to communicate via I²C Bus.
Simple-I2S
Simple I²S Master
Simple-SPI
Set of simple modules to communicate using SPI protocol.
suoglu
Config files for my GitHub profile.
suoglu.github.io
My simple personal website