hazard-detection
There are 0 repository under hazard-detection topic.
yihong1120 / Construction-Hazard-Detection
Enhances construction site safety using YOLO for object detection, identifying hazards like workers without helmets or safety vests, and proximity to machinery or vehicles. HDBSCAN clusters safety cone coordinates to create monitored zones. Post-processing algorithms improve detection accuracy.
Language:Python 328mhyousefi / MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
Language:Verilog 161- Language:Verilog 110
- eo_tools
odhondt / eo_tools
A python toolbox for easily downloading and processing Sentinel-1 SLC, Sentinel-2 and DEM data.
Language:Python 43 nicolavianello95 / RISC-V
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
Language:Verilog 14williamqwu / VE370-Pipelined-Processor
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
Language:Verilog 11- ARM-Processor
kalhorghazal / ARM-Processor
ARM Processor, Computer Architecture laboratory, University of Tehran
Language:Verilog 10 helmifraser / hazard-labelling
Python GUI-based hazard video labelling
Language:Python 3PRITHIVSAKTHIUR / Augmented-Waste-Classifier-SigLIP2
Augmented-Waste-Classifier-SigLIP2 is an image classification vision-language encoder model fine-tuned from google/siglip2-base-patch16-224
Language:Python 3qasimkhalid / SBEO
Smart Building Evacuation Ontology
arianhaddadi / ARM-Processor-32-bit
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
Language:Verilog 2Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
Language:VHDL 2rcfdtools / R.SIGE
CURSO - Taller de Sistemas de Información Geográfica aplicados a Desarrollo y Ordenamiento Territorial (OT) - SIGE
Language:Jupyter Notebook 2amaurilopez90 / LEGv8-CPU
Verilog Implementation of an ARM LEGv8 CPU
Language:Verilog 1- Language:VHDL 1
Ebimsv / Hazard-Detection-and-Captioning-System
The Hazard Detection and Captioning System uses state-of-the-art models like YOLOv11 for object detection and BLIP-based models for caption generation to analyze driver behavior and identify hazards in video streams.
Language:Python 1MiguelCPereira / EmotionalContagion
A paper exploring emotional contagion within the context of crowd simulation.
Language:C++ 1alessandromonolo / Classification-Of-Days-Exceeding-The-PM-Threshold
The research mainly aims to identify through classification algorithms if one day, based on its climatic features and concentrations of harmful elements in the air, it turns out to be harmful (or not) to the health of citizens in the Milan metropolis. A second prediction model was adopted to predict daily mean PM2.5 values.
Language:Jupyter Notebook 0FarrukhAijaz / Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design
Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor
Language:Verilog 0niosh-mining / hazardrecognitionwebsite
The Hazard Recognition Challenge allows you to perform a virtual workplace examination. Your goal is to find as many hazards as possible at a work location.
Language:JavaScript 0sushi0706 / mips-pipeline-processor
5-stage pipelined 32-bit MIPS processor
Language:Verilog 0wagerc97 / noxsensor-public
Optical sensor to detect hazardous gas in corrosive environment. Showcasing my Raspberry Pi project combining electrical engineering and sensor detection.
0- Language:VHDL
bori00 / StalledMIPS
Structure of Computer Systems course (3rd year, 1st semester)
Language:VHDL- Language:VHDL
DoniaGameel / Pipelined-Processor-using-verilog
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
Language:VerilogMahekkumar-Varasada / 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
Language:Verilog- Language:Verilog
- Language:JavaScript
