Sudhamshu B N's repositories
32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
Single-Cycle-Risc-Processor-32-bit-Verilog
Single Cycle RISC MIPS Processor
Hardware-Description-Languages-for-FPGA-Design
My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
Single-Cycle-Risc-Pipelined-Processor-Verilog
Single Cycle MIPS Pipelined Processor using Verilog
25-VLSI-Miniprojects
Implementing all aat topics given to students by college
Innovatefpga-AP049
Project for Innovatefpga contest.
sudhamshu091
My activities after July 5 2020 appear here.
sudhamshu091.github.io
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