logic-synthesis

There are 11 repositories under logic-synthesis topic.

lsils / lstools-showcase
Showcase examples for EPFL logic synthesis libraries
logic-synthesis examples
Language:CSS 162
NYU-MLDA / OpenABC
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
electronics-design logic-synthesis graph-machine-learning graph-neural-networks deep-learning datasets electronics-design-automation boolean-optimization bulls-eye openabc-d benchmarks circuit-benchmarks logic-synthesis-benchmarks
Language:Verilog 94
DRiLLS
scale-lab / DRiLLS
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
logic-synthesis reinforcement-learning abc machine-learning drills aspdac deep-learning
Language:Python 94
msoeken / cirkit
A circuit toolkit
logic-synthesis logic-gates quantum-computing reversible
Language:C++ 91
lnis-uofu / LSOracle
IDEA project source files
logic-synthesis
Language:Verilog 87
clin99 / awesome-eda
eda open-source placement routing timer logic-synthesis parser verilog circuit fpga lithography systemverilog simulation verification gds static-timing-analysis
86
bojackchen / digital-flow
This is a tutorial on standard digital design flow
timing-analysis verilog-hdl synopsys logic-synthesis synthesis
Language:Tcl 70
nbulsi / also
A logic synthesis tool
logic-synthesis majority-based-boolean-function
Language:C++ 60
workcraft / workcraft
Toolset to capture, simulate, synthesize and verify graph models
cad eda formal-specification formal-verification logic-synthesis simulation petri-nets stg fsm circuit async
Language:Java 55
fiction
cda-tum / fiction
An open-source design automation framework for Field-coupled Nanotechnologies
emerging-tech nanocomputing fcn qca layout sidb nml eda logic-synthesis placement routing verification clocking simulation
Language:C++ 53
ieee-ceda-datc / RDF-2019
DATC RDF
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation placement routing clock-tree logic-synthesis
Language:Verilog 46
scale-lab / OpenPhySyn
EDA physical synthesis optimization kit
physical-synthesis logic-synthesis physical-design optimization
Language:Verilog 46
msoeken / kitty
C++ truth table library
algorithms boolean-function logic-synthesis
Language:C++ 41
The-OpenROAD-Project / yosys
Logic synthesis and ABC based optimization
brown-university logic-synthesis physical-synthesis
Language:C++ 40
hriener / lorina
C++ parsing library for simple formats used in logic synthesis and formal verification
logic-synthesis parsing-library
Language:C++ 33
scale-lab / BLASYS
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
logic-synthesis approximate-circuits verilog approximate-computing
Language:Verilog 26
scale-lab / DRUM
The Verilog source code for DRUM approximate multiplier.
multiplier logic-synthesis approximate-circuits approximate-computing verilog
Language:Verilog 25
Chenghao-Yang / awesome-ml4ls
Awesome machine learning for logic synthesis
graph-neural-networks logic-synthesis machine-learning reinforcement-learning transformer electronic-design-automation
Language:Python 23
cornell-zhang / HOGA
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
distributed-training electronic-design-automation graph-learning graph-transformer logic-synthesis
Language:Python 19
panhomyoung / phyLS
A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
logic-synthesis
Language:C++ 13
scale-lab / BACS
Benchmarks for Approximate Circuit Synthesis
approximate-circuits benchmarks logic-synthesis verilog
Language:Verilog 12
scale-lab / ABACUS
ABACUS is a tool for approximate logic synthesis
logic-synthesis verilog synthesis approximate-computing approximate-circuits
Language:C 11
shobro / ACLA
Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
approximate-adder approximate-circuits approximate-computing computer-architecture electronic-design-automation logic-synthesis matlab verilog vlsi
Language:Verilog 11
nlwmode / Awesome-Logic-Synthesis
A collection of the Logic Synthesis about peoples/papers/projects/tutorials...
eda logic-synthesis
9
porglezomp / minecraft-eda
Electronic design automation for Minecraft
eda logic-synthesis minecraft place-and-route pnr
Language:Python 9
SJTU-ECTL / VECBEE
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
eda abc logic-synthesis approximate-computing single-selection batch-error-estimation
Language:C++ 8
anthonyabeo / digital_circuits
A collection of digital logic circuits
digital-circuit logic-design logic-synthesis systemverilog
Language:SystemVerilog 7
asyncvlsi / chp2prs
Automated conversion from CHP to PRS using syntax-directed translation
asynchronous-vlsi eda logic-design logic-synthesis
Language:C++ 7
Daikon-Sun / FRAIG
Functionally Reduced And-Inverter Graph
eda satisfiability logic-synthesis
Language:C++ 7
hriener / easy
C++ header-only ESOP library
logic-synthesis xor boolean-function esop-forms
Language:C++ 7
The-OpenROAD-Project-Attic / abc
Implementing physical synthesis and SDC support into ABC
logic-synthesis physical-synthesis brown-university
Language:C 7
porglezomp / nangate
Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
logic-synthesis nan-gate verilog yosys yosys-plugin
Language:C++ 6
boschmitt / exorcism
Fast Heuristic Minimization of Exclusive-Sums-of-Products
logic-minimization logic-synthesis
Language:C++ 5
Koyama-Tsubasa / Advanced_Logic_Synthesis
Coursework of NTHU CS613200 Advanced Logic Synthesis
blif decomposition fpga logic-synthesis technology-mapping
Language:C++ 5
SJTU-ECTL / HEDALS
Highly efficient delay-driven approximate logic synthesis
approximate-computing logic-synthesis
Language:Verilog 3
SJTU-ECTL / MECALS
An approximate logic synthesis tool under the maximum error constraint
approximate-computing logic-synthesis maximum-error
Language:Verilog 3