fault-simulation

There are 0 repository under fault-simulation topic.

litmus
litmuschaos / litmus
Litmus helps SREs and developers practice chaos engineering in a Cloud-native way. Chaos experiments are published at the ChaosHub (https://hub.litmuschaos.io). Community notes is at https://hackmd.io/a4Zu_sH4TZGeih-xCimi3Q
chaos-engineering chaos-experiments chaos-testing chaoshub cloud-native cncf devops fault-injection fault-simulation golang google-summer-of-code hacktoberfest k8s kubernetes lfx litmuschaos operator-sdk reliability-engineering resilience-testing site-reliability-engineering
Language:Go 4234
AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
atpg dft eda fault-simulation jtag scan-chains stuck-at testing verilog verilog-hdl vlsi-cad
Language:Swift 116
NTU-LaDS-II / FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
atpg eda cpp verilog stuck-at vlsi cli lex yacc fan-out test-pattern fault-simulation combinational-circuits sequential-circuits electronic-design-automation vlsi-testing
Language:Verilog 68
amamory-verification / hw-formal-verif
Hardware Formal Verification
formal-verification fault-simulation model-checking equivalence-checker jasper-gold vhdl systemverilog
Language:Verilog 13
kalexio / fault-simulator
Simple fault simulator
atpg stuck-at fault-simulation fault-injection
Language:C 6
MakisChristou / ParallelCircuitSimulator
A serial and parallel logic fault simulator on gate level netlists.
vlsi iscas simulator parallel-computing fault-simulation
Language:TeX 5
AndreasKaratzas / circuit-simulation
This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.
circuit-simulation combinational-circuit combinational-logic cpp iscas fault-simulation stuck-at c
Language:C++ 3
Mrcuve0 / TFT-RI5CY-Assignment
Source files and documentation for the final assignment of the "Testing and Fault Tolerance" course.
riscv ri5cy pulp testing atpg fault-simulation
Language:Verilog 2
cad-polito-it / r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
fault-simulation logic-simulation questasim risc-v stuck-at-faults zoix
Language:Verilog 1
intelligent-systems-lab-org / SimuNEX
A high-fidelity dynamic simulation framework.
3d-visualization actuator-dynamics control-systems dynamic-simulation event-driven-simulation high-fidelity robotics-simulation scada-system sensors fault-simulation
Language:C# 1
ucchino / caliban
A fault simulator that adopts an algorithm called "GODFATHER" created by Pier Paolo Ucchino
fault-simulation testing-tools
Language:C 0
celine-hsieh / VLSI-Testing-LAB-1
Fault Simulation | Parallel Fault Simulation | Deductive fault Simulation | Test Coverage
atpg controllability deductive-fault-simulation dft fault-simulation observability parallel-testing test-coverage
Language:Verilog