hardware-accelerator

There are 0 repository under hardware-accelerator topic.

cucapra / filament
Fearless hardware design
fpga hardware-accelerator hardware-description-language type-system
Language:Verilog 128
CMU-SAFARI / SneakySnake
SneakySnake:snake: is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs/1910.09020.
sequence-aligner fpga gpu hardware-accelerator minimap2 edlib smith-waterman needleman-wunsch pre-alignment-filtering sequence-alignment long-reads short-reads wavefront-alignment
Language:VHDL 46
Intuity / nexus
Open source RTL simulation acceleration on commodity hardware
rtl verilog systemverilog simulation hardware hardware-acceleration hardware-accelerator hardware-accelerators
Language:Python 17
yonseicasl / NeuroSpector
NeuroSpector: Dataflow and Mapping Optimization of Deep Neural Network Accelerators
accelerator deep-learning deep-neural-network hardware-accelerator machine-learning scheduling architecture dataflow mapping optimization optimizer hierarchy acceleration scheduler
Language:C++ 14
CMU-SAFARI / GenStore
GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and computational overheads of genome sequence analysis by exploiting low-cost and accurate in-storage filters. Described in the ASPLOS 2022 paper by Mansouri Ghiasi et al. at https://people.inf.ethz.ch/omutlu/pub/GenStore_asplos22-arxiv.pdf
read-mapping in-storage-processing pre-alignment-filtering exact-matching long-reads ftl hardware-accelerator sequence-alignment ssd near-data-processing
Language:C 12
yonseicasl / NPUsim
NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator
acceleration accelerator architecture cycle-accurate deep-learning deep-neural-network full-system hardware-accelerator hierarchy machine-learning memory model modeling npu simulator functional-simulation timing-simulation value-aware
Language:C++ 6
sfu-arch / muir-sim
muIR C++ Simulator
hardware-accelerator simulation verilator muir-sim dpi
Language:C++ 5
BhattSoham / Half-Precision-RK-Accelerator
Hardware Accelerator For Runge-Kutta solvers for ODE using Half Precision Floating Point Unit
hardware-accelerator ode-solver vhdl xilinx-vivado zynq-zc702
Language:VHDL
BhattSoham / Implementation-of-Runge-Kutta-Hardware-Accelerator
Hardware Accelerator implementation for solving an ordinary differential equation using Runge Kutta Numerical methods using VHDL language
computer-architecture hardware-accelerator runge-kutta vhdl xilinx-vivado zynq-zc702 ode-solvers
Language:VHDL
rbostandoust / CapNet-Accelerator
Hardware accelerator for Capsule Neural Networks
capsule-neural-networks hardware-accelerator hardware-synthesis
Language:Python

hardware-accelerator

cucapra / filament

CMU-SAFARI / SneakySnake

Intuity / nexus

yonseicasl / NeuroSpector

CMU-SAFARI / GenStore

yonseicasl / NPUsim

sfu-arch / muir-sim

BhattSoham / Half-Precision-RK-Accelerator

BhattSoham / Implementation-of-Runge-Kutta-Hardware-Accelerator

rbostandoust / CapNet-Accelerator