tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

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Dadda-Multiplier (VLSI for signal processing)

Dadda multipliers require less area and are slightly faster than Wallace tree multipliers. Among tree multipliers, Dadda multiplier is the most popular multiplier. The above code consists of (8,8), (16,16), (32,32) dadda multiplier along with self checking test bench.

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Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

License:Mozilla Public License 2.0


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Language:Verilog 98.7%Language:Coq 1.3%