There are 0 repository under arithmetic-logic-unit topic.
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.
北京邮电大学 2023-2024 春季学期《计算机组成原理》课程实验集合
Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.
Verilog description, a driver program for arithmetic logic unit for square root operation.
Computer Architecture Projects
Contains codes and designs of computer architecture assignments
This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.
Contains the project resources of the course CSE306. These were group projects.
This project implements a 4-bit ALU with six operations using Verilog on the Tang Nano 9K FPGA. It includes a detailed circuit simulation, real-life construction, and comprehensive documentation for open-source use.
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
RISC V PROCESSOR DESIGN IN VERILOG
Repository accompanying the paper "Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications" published in IEEE Transactions on Circuits and Systems II
Assignments done in CSE306 course offered by CSE, BUET
My work on the project-based course NAND2TETRIS.
A final year undergraduate major project. (Dec 2019 - Mar 2020)
This repository contains all the necessary Verilog code and supporting files to synthesize the 8-bit soft-core processor on an FPGA. The code is well-commented, following best practices in digital design to ensure clarity and maintainability.
SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project
Este proyecto se basa en la creación de dos implementaciones de unidades aritméticas lógicas (ALU) en el lenguaje NAND2TETRIS. Proyecto realizado para la asignatura "Organización de Computadores" dictada en la Universidad EAFIT.
This repository demonstrates an 8-bit Arithmetic Logic Unit (ALU) built using IoT components like a Raspberry Pi Pico, seven-segment displays, and SN74LS83N Adder ICs to perform binary addition.
Various small programs: barnsley fern, game of life, christmas tree, langton's ant, bean machine, etc.
Design and Implementation of Arithmetic Logic Unit Capable of Calculating Z=1/4(A X B)+1
A configurable Arithmetic Logic Unit (ALU) supporting 12 operations with parameterized data width. Designed with low-power techniques including clock gating and operand isolation. Simulated using Xilinx Vivado WebPACK with waveform verification.
Design a 4-bit ALU capable of performing 4 different arithmetic or logical operations using Quartus, implement it using Verilog HDL, and verify it using a timing diagram.
Verilog implementation of an N-bit ALU supporting operations like AND, OR, ADD, SUB, SLT, and functions with complemented inputs. Ideal for CPU design and digital system projects.