cpu-design

There are 2 repositories under cpu-design topic.

phoeniX-Digital-Design / phoeniX
phoeniX RISC-V Processor
cpu-design computer-architecture fpga vlsi microprocessor riscv risc-v cpu embedded-systems approximate-computing
Language:Verilog 47
CPUsimulator
mrmcsoftware / CPUsimulator
This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.
assembler assembly-language computer-simulator cpu-design cpu-simulator emulator html javascript logisim logisim-cpu logisim-evolution simulator
Language:HTML 20
Linkuit-Studio
SimonBuxx / Linkuit-Studio
A platform for learning and experimenting with logic circuits
logic simulator simulation cpu-design logic-simulator logic-simulation logic-gates logic-circuit logic-circuit-simulator logiccircuit
Language:C++ 19
rauhul / ece411
Computer Architecture UIUC SP 2018
cpu-design lc3 branch-prediction cache
Language:Assembly 9
sarthi92 / vector_processor
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
cpu-design memory vector-processor verilog
Language:Verilog 9
martandrMC / cpu-design
This repository contains files regarding my CPU designs
assembly cpu-design
Language:Verilog 6
arsalanjabbari / MIPS-CPU-Design
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
cpu-design mips single-cycle-processor
Language:Verilog 5
arsalanjabbari / RISCV-CPU-Design
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
cpu-design multicycle-processor risc-v
Language:Verilog 5
EmreKumas / Processor_Design
This is an implementation of a simple CPU in Logisim and Verilog.
address-memory alu assembler control-unit cpu cpu-design cpu-simulation data-memory instructions logisim modelsim register-file
Language:Verilog 5
FISC-Project / FISC-SystemVerilog
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
arm c computer-architecture cpp cpu cpu-design systemverilog verilog
Language:Verilog 5
sarthi92 / cpu_cisc
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
verilog cpu-design
Language:Verilog 5
ArvinDelavari / Digital-Circuits-Verilog
Sample Verilog codes for digital circuits
computer-architecture cpu cpu-design digital-design digital-design-and-computer-organization hardware-description-language hdl iverilog risc-v verilog vscode
Language:Verilog 4
ChaminduS / Building-a-RISC-V-CPU-Core
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
risc-v cpu-design digital-logic-design makerchip
4
emmapaczkowski / ELEC374
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
cpu-design risc-processor
Language:Verilog 4
naderabdalghani / 32-bit-risc-pipelined-processor
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
hardware cpu-design 32-bit pipelined-processors assembler-implementation
Language:VHDL 4
OrangeBacon / orange
Emulator for custom computer architecture
emulator c microcode microassembly assembler parser cpu-design
Language:C 4
ArvinDelavari / RV32-APX
32 Bits RISC-V Processor with Approximate Functions
approximate-computing computer-architecture computer-vision cpu-design fpga hdl risc-v rv32-apx rv32im verilog
Language:Verilog 3
MinecraftPublisher / bit
A simple, Turing-complete and easy to recreate CPU architecture.
cpu cpu-design cpu-emulator emulator virtual-machine
Language:HTML 3
mrmcsoftware / MyCPUfiles
These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.
assembly-language cpu cpu-design cpu-simulation fpga logisim logisim-computer logisim-cpu logisim-evolution videos youtube cpu-instruction-set
Language:HTML 3
joonicks / BizzasCPU
Bizzas CPU design
fpga cpu-design quartus quartus2 8-bit-cpu
Language:C 2
AliAtaollahi / Computer-Architecture-Course-Projects
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022
cpu-design hardware-designs hdl instruction-set-simulator mips mips-assembly
Language:Verilog 1
arashsm79 / mips-hdl
Single-cycle and multi-cycle implementation of a subset of MIPS instruction set
mips single-cycle multi-cycle assembly mips-architecture mips-cpu cpu-design verilog hdl
Language:Verilog 1
BrentSeidel / VHDL-CPU
VHDL Design for a CPU
arduino cpu-design vhdl
Language:C 1
FISC-Project / FISC-Microlang
FISC-Microlang is a low level language below Assembly. It is used in the FISC project for creating the Microcode memory.
armv8 assembly computer-architecture cpu-design low-level-language microcode-memory
Language:M4 1
HappyFakeBoulder / FreeCPU-HARM8
An open-source design for an 8-bit RISC CPU
cpu-design cpu-simulator logisim open-source python3
Language:Python 1
MarkArranz / nand2tetris
Building a computer from first principles. Logic Gates -> CPU Architecture -> Machine Language -> VM -> High-Level Language -> Compiler -> OS -> DS & A
assembler-implementation compiler compiler-design cpu-design hardware logic-gates machine-language memory-management virtual-machine-implementation
Language:Hack 1
moreda-a / CPU-Design-RISC
Computer Architecture Project
computer-architecture cpu-design
Language:VHDL 1
phoeniX-Digital-Design / .github
computer-architecture cpu-design digital-design embedded-systems fpga risc-v riscv software-development vlsi
1
SamEThibault / elec-374
Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering
cpu-design risc-processor verilog
Language:Verilog 1
sarthi92 / cpu_risc
Verilog implementation of 16-bit RISC Processor with 4-stage pipeline
verilog cpu-design risc-processor
Language:Verilog 1
The-Little-Light / SYSU_computer
大二上计组实验,包含32位mips指令集单周期CPU,多周期CPU,五级流水线(支持旁路与硬件级阻塞)CPU以及mips指令汇编器
sysu cpu mips-cpu cpu-design
Language:C++ 1
marcotulio956 / boring.cyclesLAOCII
computer-architecture computer-organization multicicle computer-engineering central-processing-unit cpu-design verilog fpga
Language:Verilog 0
mehmetakifkoz / CENG3010-Computer-Organization
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
16-bit-cpu code-execution computer-architecture control-unit cpu-design custom-processor gui-dashboard instruction-set-architecture logic-circuits mips-simulator processor-design simulation user-interface
Language:JavaScript 0
q-datum / Single-Cycle-RISC-V-Processor
RV32I architecture implemented in Verilog
cpu-design risc-v verilog
Language:Verilog 0
Russellwzr / Design-and-implementation-of-a-simple-CPU
Design-and-implementation-of-a-simple-CPU
cpu-design fpga quartus
Language:VHDL 0
VahidHeidari / CPU-E-bity
4-bit CPU designed with discrete components and 74-series ICs.
2-pass-assembler 4-bit-cpu 74-series cpu-design discrete-components
Language:HTML

cpu-design

phoeniX-Digital-Design / phoeniX

mrmcsoftware / CPUsimulator

SimonBuxx / Linkuit-Studio

rauhul / ece411

sarthi92 / vector_processor

martandrMC / cpu-design

arsalanjabbari / MIPS-CPU-Design

arsalanjabbari / RISCV-CPU-Design

EmreKumas / Processor_Design

FISC-Project / FISC-SystemVerilog

sarthi92 / cpu_cisc

ArvinDelavari / Digital-Circuits-Verilog

ChaminduS / Building-a-RISC-V-CPU-Core

emmapaczkowski / ELEC374

naderabdalghani / 32-bit-risc-pipelined-processor

OrangeBacon / orange

ArvinDelavari / RV32-APX

MinecraftPublisher / bit

mrmcsoftware / MyCPUfiles

joonicks / BizzasCPU

AliAtaollahi / Computer-Architecture-Course-Projects

arashsm79 / mips-hdl

BrentSeidel / VHDL-CPU

FISC-Project / FISC-Microlang

HappyFakeBoulder / FreeCPU-HARM8

MarkArranz / nand2tetris

moreda-a / CPU-Design-RISC

phoeniX-Digital-Design / .github

SamEThibault / elec-374

sarthi92 / cpu_risc

The-Little-Light / SYSU_computer

marcotulio956 / boring.cyclesLAOCII

mehmetakifkoz / CENG3010-Computer-Organization

q-datum / Single-Cycle-RISC-V-Processor

Russellwzr / Design-and-implementation-of-a-simple-CPU

VahidHeidari / CPU-E-bity