cpu-design

There are 2 repositories under cpu-design topic.

phoeniX-Digital-Design / phoeniX
A Reconfigurable RISC-V Core for Approximate Computing
cpu-design computer-architecture fpga vlsi microprocessor riscv risc-v cpu embedded-systems approximate-computing
Language:Verilog 125
CPUsimulator
mrmcsoftware / CPUsimulator
This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.
assembler assembly-language computer-simulator cpu-design cpu-simulator emulator html javascript logisim logisim-cpu logisim-evolution simulator
Language:HTML 35
Linkuit-Studio
SimonBuxx / Linkuit-Studio
A platform for learning and experimenting with logic circuits
logic simulator simulation cpu-design logic-simulator logic-simulation logic-gates logic-circuit logic-circuit-simulator logiccircuit
Language:C++ 25
rauhul / ece411
Computer Architecture UIUC SP 2018
cpu-design lc3 branch-prediction cache
Language:Assembly 13
sarthi92 / vector_processor
Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor
verilog cpu-design vector-processor memory
Language:Verilog 10
arsalanjabbari / RISCV-CPU-Design
In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
cpu-design multicycle-processor risc-v
Language:Verilog 8
sarthi92 / cpu_cisc
Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme
verilog cpu-design
Language:Verilog 7
ChaminduS / Building-a-RISC-V-CPU-Core
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
risc-v cpu-design digital-logic-design makerchip
6
martandrMC / cpu-design
Aggreage of my past CPU designs.
cpu-design assembly-language java systemverilog verilog
Language:Verilog 6
arsalanjabbari / MIPS-CPU-Design
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
cpu-design mips single-cycle-processor
Language:Verilog 5
ArvinDelavari / Digital-Circuits-Verilog
Sample Verilog codes for digital circuits
computer-architecture cpu cpu-design digital-design digital-design-and-computer-organization hardware-description-language hdl iverilog risc-v verilog vscode
Language:Verilog 5
emmapaczkowski / ELEC374
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
risc-processor cpu-design
Language:Verilog 5
EmreKumas / Processor_Design
This is an implementation of a simple CPU in Logisim and Verilog.
cpu cpu-design cpu-simulation register-file data-memory address-memory instructions alu control-unit assembler logisim modelsim
Language:Verilog 5
FISC-Project / FISC-SystemVerilog
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
arm cpu computer-architecture cpu-design verilog systemverilog c cpp
Language:Verilog 5
mrmcsoftware / MyCPUfiles
These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.
assembly-language cpu cpu-design cpu-simulation fpga logisim logisim-computer logisim-cpu logisim-evolution videos youtube cpu-instruction-set
Language:HTML 5
naderabdalghani / 32-bit-risc-pipelined-processor
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
hardware cpu-design 32-bit pipelined-processors assembler-implementation
Language:VHDL 5
bsod2528 / cpu
a simple risc processor
cpu-design rtl vlsi
Language:Verilog 4
OrangeBacon / orange
Emulator for custom computer architecture
emulator c microcode microassembly assembler parser cpu-design
Language:C 4
BrentSeidel / VHDL-CPU
VHDL Design for a CPU
cpu-design vhdl arduino
Language:C 3
Danijel-Korent / homemade-CPU
designing a 8-bit CPU for fun
8-bit cpu cpu-design cpu-simulation cpu-simulator digital-electronics digital-logic digital-logic-design logisim logisim-cpu
Language:Assembly 3
MinecraftPublisher / bit
A simple, Turing-complete and easy to recreate CPU architecture.
cpu cpu-design cpu-emulator emulator virtual-machine
Language:HTML 3
AliAtaollahi / Computer-Architecture-Course-Projects
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022
cpu-design hardware-designs hdl instruction-set-simulator mips mips-assembly
Language:Verilog 2
joonicks / BizzasCPU
Bizzas CPU design
fpga cpu-design quartus quartus2 8-bit-cpu
Language:C 2
JuanCantu1 / CPU-Design
Python-based simulator for a 24-bit RISC processor with a five-stage pipeline. Focused on instruction-level, cycle-accurate modeling.
computer-architecture cpu-design python risc-v verilog
Language:SystemVerilog 2
Karan-nevage / RISC-V-Single-Cycle-Core-Verilog-
This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.
alu control-unit cpu-design risc-v verilog verilog-project vlsi
Language:JavaScript 2
aegirontechnologies / vireon-dev-kit
AEGIS Libre Developers Kit
armv9 cpu-design ddr5 firmware open-hardware
Language:HTML 1
alissonjsb4 / 8-bit-cpu-and-assembler-toolchain
An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.
academic-project assembler c-plus-plus compiler computer-architecture cpu-design custom-isa fpga hardware-software-co-design processor rtl-design toolchain verilog
Language:Verilog 1
Danial-Changez / 16-Bit-MIPS-CPU
Collaborative project using Vivado to design a CPU capable of executing R, I, and J instructions with scalable architecture.
computer-architecture cpu-design mips risc-architecture-processor vhdl vivado
Language:VHDL 1
itworks99 / vtx1
Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication
balanced-ternary cpu-design digital-design fpga icarus-verilog microcode open-hardware processor-architecture processor-design rtl-design soc synthesis system-on-chip system-on-chip-design ternary ternary-computer vliw yosys
Language:Verilog 1
kyriosaa / sap-1
A fully functional 8-bit computer built entirely from scratch using basic logic chips & breadboards
8-bit-computer computer-architecture cpu-design
Language:Assembly 1
mauroxf / Verilog_Pipelined_CPU
A modular 3-stage RISC CPU in Verilog with fetch, decode, and execute stages, supporting core ALU operations.
cpu-design pipeline risc-v verilog
Language:Verilog 1
mehmetakifkoz / MARS-Web-App
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
16-bit-cpu code-execution computer-architecture control-unit cpu-design custom-processor gui-dashboard instruction-set-architecture logic-circuits mips-simulator processor-design simulation user-interface
Language:JavaScript 1
mo2menwael / MIPS32_Pipelined_Processor
A Verilog-implemented MIPS32 pipelined processor featuring a 2-bit branch predictor and an exception handling unit, supporting over 50 instructions including arithmetic, logic, branch, memory, and control operations.
computer-architecture cpu-design mips rtl verilog
Language:Verilog 1
mrFavoslav / 4bit-cpu-emulator
4bit CPU Emulator – A simple 4-bit processor emulator written in JavaScript. Run assembly code directly in your browser! Perfect for learning the basics of computer architecture and low-level programming.
4-bit-cpu assembler assembly assembly-language computer-architecture cpu-design cpu-emulator educational emulator javascript learning-tool low-level-programming open-source programming simulation web-emulator
Language:JavaScript 1
naymilikeschoco / miniLA_CPU_design
HITSZ_2025_Summer_CS_miniLA_cpu_design
cpu-design
Language:Verilog 1
panoskoutris / riscv-cpu
Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.
computer-architecture cpu-design digital-design eda-playground fpga fsm hardware hdl icarus-verilog processor-design risc-v simulation verilog testbench
Language:Verilog 1

cpu-design

phoeniX-Digital-Design / phoeniX

mrmcsoftware / CPUsimulator

SimonBuxx / Linkuit-Studio

rauhul / ece411

sarthi92 / vector_processor

arsalanjabbari / RISCV-CPU-Design

sarthi92 / cpu_cisc

ChaminduS / Building-a-RISC-V-CPU-Core

martandrMC / cpu-design

arsalanjabbari / MIPS-CPU-Design

ArvinDelavari / Digital-Circuits-Verilog

emmapaczkowski / ELEC374

EmreKumas / Processor_Design

FISC-Project / FISC-SystemVerilog

mrmcsoftware / MyCPUfiles

naderabdalghani / 32-bit-risc-pipelined-processor

bsod2528 / cpu

OrangeBacon / orange

BrentSeidel / VHDL-CPU

Danijel-Korent / homemade-CPU

MinecraftPublisher / bit

AliAtaollahi / Computer-Architecture-Course-Projects

joonicks / BizzasCPU

JuanCantu1 / CPU-Design

Karan-nevage / RISC-V-Single-Cycle-Core-Verilog-

aegirontechnologies / vireon-dev-kit

alissonjsb4 / 8-bit-cpu-and-assembler-toolchain

Danial-Changez / 16-Bit-MIPS-CPU

itworks99 / vtx1

kyriosaa / sap-1

mauroxf / Verilog_Pipelined_CPU

mehmetakifkoz / MARS-Web-App

mo2menwael / MIPS32_Pipelined_Processor

mrFavoslav / 4bit-cpu-emulator

naymilikeschoco / miniLA_CPU_design

panoskoutris / riscv-cpu