meiniKi

FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

SimIO

SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

RV32I_SC_Logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

tt06-FazyRV-ExoTiny

flexbex

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

FazyRV-ExoTiny

GameGrid64

GameGrid64 is a 64x64 LED Matrix gaming console that was created as a weekend project.

Streamliner

tt03-another-piece-of-pi

Tiny Tapeout 03: Another Piece of Pi

blog_yosyshq

edalize

An abstraction library for interfacing EDA tools

litex

Build your hardware, easily!

Checkr

A minimalistic UI for grammar correction with self-hosted AI.

clash-ethernet

A fully configurable Ethernet core written in Clash.

cocktail

A model manager for Civitai

corescore

CoreScore

esphome-sound-level-meter

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

JSON.sv

SystemVerilog package for reading, manipulating, and writing JSON-formatted data

micropython

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

nextpnr

nextpnr portable FPGA place and route tool

nextpnr-tests

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Paper2Go

Paper2Go converts documents to an AI-summarized audiobook.

qerv

sock.sv

A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.

thinkpad-paint-cover

tt05-submission-template

Submission template for Tiny Tapeout 05

ttihp-FazyRV-ExoTiny