There are 4 repositories under hspice topic.
HSPICE and MATLAB simulation files of a tracking SAR ADC
Modified Nodal Analysis by using MATLAB
NGSPICE Simulation of CMOS Circuits
This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.
This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect tradeoff between the contradictory objective functions in CMOS RO optimal design. This tool is applied for intelligent estimation of the circuit parameters (channel width of transistors), which have a decisive influence on RO specifications. Along the optimal RO design in an specified range of oscillaton frequency, the Power Consumption, Phase Noise, Figure of Merit (FoM), Integration Index, Design Cycle Time are considered as objective functions. Also, in generation of Pareto front some important issues, i.e. Overall Nondominated Vector Generation (ONVG), and Spacing (S) are considered for more effectiveness of the obtained feasible solutions in application. Four optimization algorithms called Multi-Objective Genetic Algorithm (MOGA), Multi-Objective Inclined Planes system Optimization (MOIPO), Multi-Objective Particle Swarm Optimization (MOPSO) and Multi-Objective Modified Inclined Planes System Optimization (MOMIPO) are utilized for 0.18-mm CMOS technology with supply voltage of 1-V. Baesd on our extensive simulations and experimental results MOMIPO outperforms the best performance among other multi-objective algorithms in presented RO designing tool.
FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)
HSPICE implementation of hybrid CMOS/Memristor BAM
Script that automates the process to create multiple Spice files through copying and appending. Each file is ran through subprocess and HSPICE, output is saved to find min Time Delay.
grayscale conversion system and simple convolution system
Assignment of Microelectronic Circuits using HSPICE to simulate some of CMOS gates logics.
An easy to use GUI for multi-objective optimization of electrical and electronic circuits using evolutionary and heuristic algorithms and HSPICE.
Principle of electronics is one of the undergraduate courses in Sharif university of technology that is about analysis and design amplifying electronic circuits
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
FuzzyIWO-Algorithm (Adaptive fuzzy optimisation algorithm)
FinFET Registers - Instituto de Informática da UFRGS
We were required to design a "fully differential OpAmp" with some analysis, including open-loop gain ones and closed-loop ones in common-mode and differential-mode. Moreover, we simulated it with DC sweep, AC response, response with step, in order to obtain the waveform and check whether our design achieved the specification.
This frequency divider is able to divide the clock signal depending on 3-bit input signal. Also, we were required to draw block diagrams to represent the structure, use “laker” to layout, use another software to simulate the different after doing layout, and analyze delay and power consumption.
A center of gravity defuzzifier implemented as an analog CMOS circuit
An analog circuit of a neural network to be used as a weighted order statistic filter
A parallel-prefix adder implemented using Ling’s transformation.
Multiplier is one of the most important arithmetic unit in Microprocessors and DSPs and also a major source of power dissipation. Reducing the power dissipation of multipliers is a key to satisfy the overall power budget of various digital circuits and systems. The project elaborates the steps required to design array multiplier. The fundamental units to design a multiplier are adders. The variants of adders used in this project are Carry Save Adder(CSA) and Carry Propagate Adder(CPA). The main objective of our work is to calculate the average power, delay and PDP of 4x4 multipliers. The design of Half adder and Full adder for low power is obtained and the low power units are implemented on the array multiplier and the results are analyzed for better performance. The designs are done using Mentor Graphics tool and are simulated using H-SPICE
NTUEE IC Design 23Fall HW2
This project demonstrates how to use python to analyze HSpice simulation data.
Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects
This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coordinates. Optical or Infrared Angle-of-Arrival , AOA, (noisy) measurements from each anchor to the uknown target are assumed available.
A frequency divider implemented using true single-phase clock (TSPC).
This project is a part of the report for my 7th semester program elective (EC-4152 Low Power VLSI Design).
Hpice Projects including DRAM, SRAM, High-Frequency Divider and Manchester Adder.
Implementation of 2-bit & 8-bit CMOS microelectronic circuit simulations in HSpice