qflow

There are 0 repository under qflow topic.

• aidangoettsch / asg

  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.

  edaeeschemaqflowschematics
  Language:Python 18

• efabless / ravenna

  32-bit RISC-V microcontroller

  riscvrisc-vopensourceqflowmagicvlsivlsi-design
  Language:C 11

• vsdip / vsdflow

  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

  rtlprogrammervsdipsemiconductoropensourcesynthesisyosysqflowmagicgraywolfqrouternetgenopentimeropenstablifffanouttclphysicaldesignstaticstascripting-language
  Language:Coq 11

• vishnuvardhan-k / vsd-physical-design-using-open-source-tools

  The repository shows the 5 - day wrokshop for beginners using open source tools like yosys, magic, opentimer, qrouter and the purpose of this repository is to provide a complete idea about the 5 - days workshop on VLSI SoC/Physical design using open source EDA tools.

  chip-arealayoutngspiceopentimerqflowqflow-managerqroutersynthesistkcon-windowvsd-iatyosys
  2

• brown9804 / Designs_Verification

  Here you can find different verifications, time analysis, etc.

  analysisaspectsdesigns-verificationqflowverilog
  Language:Verilog 1

• majabojarska / verilog-prefix-adder

  6-bit prefix adder implemented via Verilog HDL.

  verilogprefix-adderqflow
  Language:Verilog