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siliconcompiler

siliconcompiler

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The Silicon Compiler Project

Home Page:https://www.siliconcompiler.com

Twitter:@siliconcompiler

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siliconcompiler's repositories

siliconcompiler

A modular build system for hardware

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zerosoc

Demo SoC for SiliconCompiler.

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lambdalib

Hardware abstraction library

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lambdapdk

Library of open source Process Design Kits (PDKs)

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scgallery

SiliconCompiler Design Gallery

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sc-rfcs

RFCs for changes to SiliconCompiler

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sc-education

Educational material

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cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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caravel_wrapper_heartbeat_example

This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a format that allows the MPW pre-tapeout checks to be run on the design.

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common_cells

Common SystemVerilog components

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fossi-foundation.github.io

FOSSi Foundation Website

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OpenROAD-flow-scripts

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Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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sc-leflib

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