siliconcompiler

siliconcompiler

Modular hardware build system

zerosoc

Demo SoC for SiliconCompiler.

lambdapdk

Library of open source Process Design Kits (PDKs)

logik

A configurable RTL to bitstream FPGA toolchain

scgallery

SiliconCompiler Design Gallery

lambdalib

Hardware abstraction library

logiklib

Library of FPGA architectures

sc-rfcs

RFCs for changes to SiliconCompiler

sc-education

Educational material

sc-leflib

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

sc-surelog

caravel_wrapper_heartbeat_example

This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a format that allows the MPW pre-tapeout checks to be run on the design.

common_cells

Common SystemVerilog components

fossi-foundation.github.io

FOSSi Foundation Website

OpenROAD-flow-scripts

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX