jamieiles

80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

oldland-cpu

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

uart

Verilog UART

rpi-gdb

Raspberry Pi GDB remote serial protocol stub

fpga-cmake

Building FPGAs with Quartus+CMake

oldland-sdram

SDR SDRAM controller

a5-1-wb-macro

A5/1 Wishbone macro for Caravel ZeroToAsic group submission

linux-picoxcell

Picochip picoXcell kernel tree

multi_project_tools

riscv-compliance

riscv-tests

u-boot-oldland

u-boot port for the Oldland CPU

verilator

Verilator open-source SystemVerilog simulator and lint system

binutils-gdb-oldland

Oldland CPU binutils+gdb port

binutils-oldland

Port of binutils for the Oldland CPU architecture

cocotbext-wishbone

docker-apt-cacher-ng

Dockerfile to create a Docker container image for Apt-Cacher NG

gcc-oldland

GCC retarget for Oldland CPU

googletest

Google Test

jamieiles

Config files for my GitHub profile.

jtag

simple commandline jtag stuff

linux

Linux kernel source tree

newlib-oldland

Newlib C library for the Oldland CPU

oldland-clock

Oldland CPU demo clock

oldland-docker

Dockerfiles for Oldland CPU build environments

oldland-kernel

Simple kernel for the Oldland CPU

oldland-web

Jekyll site for Oldland CPU

opensbi-rxv

rtems-oldland

RTEMS for the Oldland CPU

vim-gtest

Vim plugin to quickly select and run GoogleTest asyncronously.