OpenTimer

OpenTimer

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A High-performance Timing Analysis Tool for VLSI systems

Location:University of Illinois at Urbana-Champaign

Home Page:https://github.com/OpenTimer

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OpenTimer's repositories

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language:VerilogLicense:NOASSERTIONStargazers:516Issues:47Issues:70

Parser-Verilog

A Standalone Structural Verilog Parser

Language:VerilogLicense:MITStargazers:77Issues:8Issues:8

Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Language:C++License:MITStargazers:47Issues:7Issues:3