rodrigomelo9

FOSS-for-FPGAs

A getting started presentation (with examples) about how to use FLOSS for FPGA development.

vivado-notes

Notes about how to perform uncommon things with Vivado

zynq-pl-ps

PL-PS data exchange in Zynq devices

zynq-examples

General-purpose examples based on Zynq (7000, UltraScale+) devices from Xilinx

zynq-petalinux

Zynq (ZCU102, Zynq US+) Petalinux Example

rodrigomelo9

My personal repository

digital-design

docker

Scripts to build and use docker images including GHDL

amba

A presentation about Advanced Microcontroller Bus Architecture

awesome

A curated list of awesome resources for HDL design and verification

btd

A multi-version Sphinx building tool, based on docker images and shell scripts

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

constraints

Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards

containers

Building and deploying container images for open source electronic design automation (EDA)

corescore

CoreScore

ghdl

VHDL 2008/93/87 simulator

ghdl-yosys-plugin

VHDL synthesis (based on ghdl)

hyperledger-recipes

min_night

An easy on the eyes Hugo blog theme with dark mode.

optimuslogic

profile repo

reveal-md

reveal.js on steroids! Get beautiful reveal.js presentations from any Markdown file

symbiflow-examples

Example designs showing different ways to use SymbiFlow toolchains.

tdd-intro

Example of Test Driven Design with VUnit

Termux-packages

Electronic design automation (EDA) package recipes for Termux (Android)

uvm-python

UVM 1.2 port to Python

vboard

Virtual development board for HDL design

vhdl-cfg

Playground to explore and compare how configuration is handled by different tools for development of VHDL projects

vivado-sta

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

wavedrom

:ocean: Digital timing diagram rendering engine