dram

There are 2 repositories under dram topic.

liquidctl / liquidctl
Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
corsair evga nzxt liquid-cooler fan-controller power-supply led-controller gigabyte asus dram graphics-card aquacomputer cross-platform driver python
Language:Python 2433
PlatformLab / RAMCloud
**No Longer Maintained** Official RAMCloud repo
dram fault-tolerance key-value low-latency storage
Language:C++ 492
CMU-SAFARI / ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
dram memory simulation
Language:C++ 391
umd-memsys / DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
simulator c-plus-plus dram computer-architecture
Language:C++ 279
CMU-SAFARI / DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
dram fpga rowhammer testing
Language:VHDL 96
mjlaine / mcmcstat
MCMC toolbox for Matlab
mcmc matlab metropolis-hastings adaptive-mcmc dram
Language:MATLAB 90
hdl-util / sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
sdram dram controller systemverilog as4c4m16sa fpga quartus
Language:Verilog 80
blark / a500plus-chipram-expansion
A 1MB chip RAM expansion for the A500+
amiga amiga-hardware dram retrocomputing a500
29
tukl-msd / DRAMSpec
A High-Level DRAM Timing, Power and Area Exploration Tool
currents dram estimation timings
Language:C++ 28
llopis / dram-tester
Sample Arduino program to test 4164 DRAM chips.
arduino dram 4164
Language:C++ 21
CMU-SAFARI / BEER
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
reliability error-correcting-codes hamming-code linear-block-code ecc-schemes experimental-data error-characteristics dram
Language:C++ 19
dovedevic / blimp
A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
blimp compilers dram processing-in-memory risc-v simulation-framework
Language:C 18
iisys-sns / FlippyRAM
FlippyRAM is an automated framework for testing and analyzing Rowhammer vulnerabilities in DRAM. It combines rowhammer tools and supports both Docker and ISO-based execution, making it a powerful resource for hardware security research.
c cpp cybersecurity dram flippyram hardware-security rowhammer security shell-scripting
Language:C++ 13
CMU-SAFARI / CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
circuit-model dram dram-latency dram-array-architecture
Language:AGS Script 12
CMU-SAFARI / EINSim
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
dram reliability error-correction error-correcting-codes map-estimation statistical-inference simulator
Language:C++ 10
saiteja-talluri / Microarchitectural-attacks
Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
rsa flush-reload cache dram
Language:C 10
wgurecky / bipymc
Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.
bayesian-inference bayesian inference mcmc mcmc-sampler gaussian-process-regression bayesian-optimization mpi4py mpi mcmc-sampling dream python dram
Language:Python 10
CMU-SAFARI / DIVA-DRAM
This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf
dram reliability
Language:AGS Script 9
CMU-SAFARI / DRAM-Datasheet-Survey
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
datasheets dram memory survey
9
ppieczul / c386sx-lt-2mb-memory-module
Commodore C386SX-LT 2MB memory module schematics
commodore dram memory vintage-computers
9
CMU-SAFARI / DRAM-Voltage-Study
Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
dram experimental-data memory memory-analysis memory-test voltage-scaling voltage memory-latency reliability reliability-data memory-systems dram-characterization energy power performance
Language:AGS Script 8
comsec-group / REM
REGA Model (REM), an accurate DRAM model.
dram model rowhammer
Language:AGS Script 8
adarshpatil / dve
Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
replication dram reliability sockets coherence
Language:Objective-C 7
adarshpatil / gem5gpu-hashcache
HAShCache + Intergrated CPU/GPU system simulation setup
simulator gpu cpu dram cache hashcache
Language:C++ 7
CMU-SAFARI / HARP
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/2109.12697.
simulator reliability dram error-correcting-codes error-correction monte-carlo
Language:C++ 7
cdslaborg / paramontex
This is a repository for the ParaMonte library examples. For more information, visit:
mcmc mcmc-sampler mcmc-methods visualization bayesian-inference bayesian bayesian-statistics bayesian-methods bayesian-optimization dram parallel markov-chain c cpp fortran fortran2018 matlab python machine-learning paramonte-library
Language:Jupyter Notebook 6
pjattke / awesome-rowhammer
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
academic attacks awesome-list ddr3 ddr4 ddr5 defenses dram hardware-security rowhammer hardware-attacks
5
johnzl-777 / DRAMutils
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
dram retro arduino arduino-library arduino-uno
Language:C++ 4
Stephen-Arsenault / DRAM-Liberator
DRAM Tester Shield for Arduino Nano
arduino dram opensource 4164
Language:C++ 3
therealczr15 / NYCU_ICLAB_2024S
Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)
apr axi4-protocol cell-based combinational-circuit cross-clock-domain dram finite-state-machine jaspergold pipeline rtl sequential-circuits sram systemverilog verilog digital-ic-design
Language:Verilog 3
gaomy3832 / energydram
DRAM energy calculation.
dram energy
Language:Python 2
ThexXTURBOXx / Raspberry-Pi-DRAM-PUF
Decay-based DRAM PUF for the Raspberry Pi 3B+ implemented on top of rpi-open-firmware
dram dram-puf firmware kernel puf raspberry-pi
Language:C 2
GauravJain28 / CPU-and-DRAM-Simulator
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
dram mips-assembly architecture
Language:C++ 1
JakubKajzer / Trugbild
An FPGA working in serial with HDMI, for some real live video modifications
dram flash fpga hdmi highspeed kicad memory pcb pcb-design ram serial trugbild xilinx xilinx-fpga
1
jtsimons / DRAMC
Behavioral architecture of a read/write cycle controller for a DRAM chip.
digital-design dram fpga memory-controller memory-design tcl vhdl
Language:VHDL 1
Lougous / simm30
30 pins DRAM memory module
dram memory module simm
1

dram

liquidctl / liquidctl

PlatformLab / RAMCloud

CMU-SAFARI / ramulator2

umd-memsys / DRAMSim2

CMU-SAFARI / DRAM-Bender

mjlaine / mcmcstat

hdl-util / sdram-controller

blark / a500plus-chipram-expansion

tukl-msd / DRAMSpec

llopis / dram-tester

CMU-SAFARI / BEER

dovedevic / blimp

iisys-sns / FlippyRAM

CMU-SAFARI / CLRDRAM

CMU-SAFARI / EINSim

saiteja-talluri / Microarchitectural-attacks

wgurecky / bipymc

CMU-SAFARI / DIVA-DRAM

CMU-SAFARI / DRAM-Datasheet-Survey

ppieczul / c386sx-lt-2mb-memory-module

CMU-SAFARI / DRAM-Voltage-Study

comsec-group / REM

adarshpatil / dve

adarshpatil / gem5gpu-hashcache

CMU-SAFARI / HARP

cdslaborg / paramontex

pjattke / awesome-rowhammer

johnzl-777 / DRAMutils

Stephen-Arsenault / DRAM-Liberator

therealczr15 / NYCU_ICLAB_2024S

gaomy3832 / energydram

ThexXTURBOXx / Raspberry-Pi-DRAM-PUF

GauravJain28 / CPU-and-DRAM-Simulator

JakubKajzer / Trugbild

jtsimons / DRAMC

Lougous / simm30