gate-level

There are 0 repository under gate-level topic.

RISC-V-CPU
jasonlin316 / RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
risc-v riscv32 gate-level place-and-route vector processor chip tape-out verilog
Language:Verilog 94
A-Single-Path-Delay-32-Point-FFT-Processor
jasonlin316 / A-Single-Path-Delay-32-Point-FFT-Processor
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
single-path-delay fft dsp pipeline processor verilog gate-level snr radix-2 butterfly
Language:Verilog 36
cad-polito-it / fenice
Customizable fault-simulation and gate-level editing library for sequential circuits
simulation event-driven cad gate-level
Language:C 6
gonsie / gates
Gate-level circuit model for ROSS
c circuit gate-level ross simulation discrete-events-simulations
Language:C 6
alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
image-processing object-oriented object-oriented-programming system-modeling systemc systemc-ams gate-level gate-level-simulation rtl-design
Language:C++ 2
Archfx / TrojanWars
TrojanWars🐎 - Test Generation for activation of malicious hardware implants
hardware gate-level rtl security trojans verilog
Language:C 2
Aliiiw / Computer-Architecture-project
implement mips cpu in python
gate-level postgresql python
Language:Python 1
shawntsai0312 / NTUEE_ICDESIGN_23FALL_HW3
NTUEE IC Design 23Fall HW3
gate-level ic ic-design logic-gates ntu ntuee poker verilog
Language:Verilog 1
shawntsai0312 / NTUEE_ICDESIGN_23FALL_HW4
NTUEE IC Design 23Fall HW4
approximation gate-level ic ic-design logic-gates ntu ntuee sigmoid verilog
Language:Verilog 1
FarshidKeivanian / Optimization-of-JK-Flip-Flop-Layout-with-Minimal-Average-Power-of-Consumption-based-on-ACOR-Fuzzy-A
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
adaptive-fuzzy-logic ant-colony-algorithm ant-colony-optimisation ant-colony-optimization cmos-circuits electronics-design flipflop fuzzy-logic gate-level gate-level-simulation jkflipflop layout layouts optimisation optimisation-algorithms optimization powerconsumption fuzzy-adaptive layout-design optimum-layout
Language:MATLAB 0
gate_level
FPGA-Systems / gate_level
Реализация элементов цифровых схем из базовых логических элементов
basic-logic fpga gate-level verilog vhdl
Language:VHDL