Amichai Ben-David's repositories
riscv-multi-core-lotr
RISCV core RV32I/E.4 threads in a ring architecture
CPUGarageChallenge
Intel CPU Garage Challenge
abd_dino_game
Testing the dino game in python so i can train a NN to and get the weights & biases for my RISCV C program.
abd_python_playground
This is my first python playground. will be used to learn basic python
CPUGarageChallenge_2
Intel CPUGarage Challenge #2
rvc_playground
RISCV Core - Designing a RISCV Core HW & simulation env.
smart_uart_playground
A System Verilog project - accessing any memory map from Host to device (FPGA) using uart - without a CPU to control the uart traffic
vga_fpga_playground
VGA FPGA Playground