instruction-decoding

There are 1 repository under instruction-decoding topic.

RVVM
LekKit / RVVM
The RISC-V Virtual Machine
c emulation emulator emulators instruction-decoding jit linux risc risc-v riscv riscv-emulator riscv-linux riscv-simulator riscv32 riscv64 rvvm tracing-jit translation virtual-machine vm
Language:C 1133
DispatchCode / x64-Instruction-Decoder
An x86/x64 instruction disassembler written in C
c instruction-decoding instruction-set assembly x86 x64 machine-code low-level architectures disassembler disassembler-library reverse-engineering
Language:C 32
CGuardProbe
OPSphystech420 / CGuardProbe
Memory Engine and Scanner for iOS/MacOS using Mach API
error-logging ios mach-o macos memory ida memory-scanning vmt-hooking reverse-engineering api hooks instruction-decoding security cpp
Language:C++ 14
Danijel-Korent / RISC-V-emulator
RISC-V emulator/simulator in Python
bare-metal baremetal instruction-decoding python python3 risc-v riscv riscv-emulator riscv-linux riscv-simulator riscv32 system-emulation cpu cpu-simulator education processor-architecture risc-v-emulator risc-v-simulator rv32ima
Language:Python 9
BeRo1985 / pasriscv
PasRISCV is a RV64GC RISC-V emulator, which is implemented in Object Pascal
delphi emulator emulators freepascal instruction-decoding object-pascal pascal risc-v riscv riscv-emulator riscv-linux riscv64 virtio virtual-machine vm rv64 rv64gc
Language:Pascal 5
uros-bojanic / 8-bit-computer
[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.
logisim cpu-architecture von-neumann-architecture instruction-decoding
3
BeRo1985 / pasriscvemu
The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator
delphi emulator emulators freepascal instruction-decoding object-pascal pascal risc-v riscv riscv-emulator riscv-linux riscv64 vulkan virtio virtual-machine vm rv64gc rv64
Language:Pascal 2
keneoneth / InstrHexBinDecConvertDecoder-Release
a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA
binary-hexadecimal-converter binary-to-decimal-number-converter instruction-decoding instruction-set-architecture instructions opcodes
Language:HTML 1
leonlafa / sap1-logisim
A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.
8bit 8bitcomputer alu arithmetic-logic-unit bus-system control-sequences digital-electronics electronics electronics-engineering instruction-decoding memory-address program-counter ram registers sap-1 sap-1-computer sap1 logic-gates binary full-adder
0
christalphilip / mips-disassembler
A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.
assembly computer-architecture disassembler instruction-decoding java mips
Language:Java