riscv32im

There are 1 repository under riscv32im topic.

risc0 / risc0-lean4
A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover
lean lean4 risc-v risc0 riscv riscv32 riscv32im zero-knowledge zk-stark zkvm
Language:Lean 72
djzenma / RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
cpu hdl pipeline-cpu pipeline-processor risc risc-processor risc-v riscv-simulator riscv32 riscv32im rv32i rv32imc verilog verilog-code verilog-hdl verilog-snippets
Language:Verilog 15
merledu / buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
buraq-mini chisel3 open-mpw risc-v riscv32im
Language:Scala 11
jesseopdenbrouw / thuas-riscv
The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbb Zbs Sdext Sdtrig microcontroller
fpga hardware riscv riscv32 riscv32im rv32im soc
Language:C 5
pixelspark / rv32jit
A RISC-V (rv32imc) assembler for JITing on the ESP32
esp32 esp32-c3 risc-v riscv32 riscv32im rust
Language:Rust 4
amamory-ursa / riscv-gnu-toolchain-docker
Dockerfile for RISC-V GNU Compiler Toolchain
qemu-riscv riscv32 riscv32im
Language:Dockerfile 0
RISCuinho / emulsiV
A visual simulator, criado por @Guillaum Savaton, for teaching computer architecture using the RISC-V instruction set
risc-v riscv riscv-simulator riscv32im
Language:JavaScript

risc0 / risc0-lean4