CAD & Reliability Group's repositories
ase_riscv_gem5_sim
RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
pulpino_ri5cy_stls
Stuck-At Software Test Libraries for the pulpino-ri5cy SoC
cv32e40p_tftlab
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
IPApproX
Set of IP management tools used within the context of the PULP project
Language:PythonBSD-3-Clause000
pulpino_testing
SBST/FuSa environment for Pulpino - An open-source microcontroller system based on RISC-V
Language:CNOASSERTION000
Language:Python000
x-heep-femu-tflite-sdk
X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK) with Tensorflow Lite for Microcontrollers support.
Language:C000