CAD & Reliability Group

I99T

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

byron

Multi-purpose extensible self-adaptive optimizer and fuzzer

fenice

Customizable fault-simulation and gate-level editing library for sequential circuits

ase_riscv_gem5_sim

RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione

pulpino_ri5cy_stls

Stuck-At Software Test Libraries for the pulpino-ri5cy SoC

cv32e40p_tftlab

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

r4ves

RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.

.github

howto

A collection of howto guides

IPApproX

Set of IP management tools used within the context of the PULP project

pulpino_testing

SBST/FuSa environment for Pulpino - An open-source microcontroller system based on RISC-V

tflite-micro-x-heep

x-heep-femu-tflite-sdk

X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK) with Tensorflow Lite for Microcontrollers support.

x-heep-tflite-cfoshw24