memory-controller

There are 0 repository under memory-controller topic.

• AngeloJacobo / UberDDR3

  Opensource DDR3 Controller

  controllerddr3phyverilogmemory-controllerddr3-controllerddr3-phyfpga
  Language:Verilog 390

• someone755 / ddr3-controller

  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

  ddr3fpgamemory-controllerverilog
  Language:Verilog 75

• Elphel / eddr3

  mirror of https://git.elphel.com/Elphel/eddr3

  verilogddropen-corefpgaxilinxzynqddr3memory-controller
  Language:Verilog 41

• krzk / linux

  This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).

  linuxkernelarmarmv7armv8arm64samsungexynosodroidlinux-kernelmemory-controllersamsung-socfsdgs101gs201qualcommteslaqcomsnapdragondevicetree
  Language:C 12

• FlorianFrank / verilog_baremetal_sram_controller

  A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

  fpgamemory-controllersramverilogxilinx
  Language:Verilog 5

• yasnakateb / SdramController

  🛠 A SDRAM controller in Verilog HDL

  sdramsdram-controllerverilogverilog-hdlicarus-verilogiverilogmemory-controller
  Language:Verilog 3

• teekamkhandelwal / SRAM_Controller

  The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

  memorymemory-controllerquestasimsramsram-controllerverilogverilog-projectvivadovlsi-designsram-controller-advancedsram-features-power-security-brustmemory-managementverlog-hdlsdramsdram-controllerenhanched-sram-controller
  Language:Verilog 2

• jtsimons / DRAMC

  Behavioral architecture of a read/write cycle controller for a DRAM chip.

  digital-designdramfpgamemory-controllermemory-designtclvhdl
  Language:VHDL 1

• muditbhargava66 / NeoRAM

  Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.

  asic-designcocotbecc-memoryfpgamemory-controlleropen-source-hardwarepytestsky130sram-controllersystemverilogverificationvlsi-designmulti-port-memory
  Language:Python 1

• ganesh-rgb / FIFO

  In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM

  buffersfifomemory-controller
  Language:SystemVerilog 0

• szym-mie / vga3

  Redesign of 'vga_src' video card architcture using proper FIFOs

  clean-architecturefifoisekicadmemory-controllerrewritespartan6verilogvgavideo-card
  Language:Verilog 0