Teekam Chand Khandelwal's repositories
asynchronous_fifo
Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
memory_verification_using_system_verilog
In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component
Dual_port_ram
dual clock dual port ram using verilog and system verilog
24-12_DIGITAL_CLOCK_DESIGN_USING_VERILOG
DESIGN DIGITAL CLOCK FOR 24/12 HOURS, USING TWO BLOCKS COUNTER AND BCD TOSEVEN SEGMENT. ALL CODE WRITTEN IN VERILOG.
4X16-decoder-environment-with-coverage-
decoder design using verilog and verified using system verilog and also perform code coverage operation using questa sim
ENVIRONMENTAL-VERIFICATION-EXAMPLES
2x1 mux is verification is done using system verilog. For verification of mux all component are designed and simulated .rtl design -verilog testbench -systemverilog, tool-edaplayground and questasim
Jtag_verliog_rtl
jtag tap_controller_fsm Verilog code
two-port-switch-test
two port switch contaning router
Uart_tx_main
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.
adder_substractor
adder and substractor both are controlled by different control signal
Floating_point_32_bit_adder_sub
in this respiratory cover adder and subtractor part and containing testbench and simulation waveform
atm_project_c_code
it is the mini project in c. design of ATM machine
ATM_using_verilog
Using Verilog
fraud_detection
Building a machine learning model for fraud detection
Lending_Club_case_Study
EDA Project case study
Linear-Regression-Bike-Sharing-Assignment
linear regression model for boombike facing issue
OpenSTA
OpenSTA engine
portfolio
Minimal is a Jekyll theme for GitHub Pages
PYTHON_LERNING_EXAMPLE
In this repository added Python language basic example and 3-Minor Projects.
Verilog_based_some_application_projects
1)8-bit ALU with all flags 2) synchronous fifo