systolic-arrays

There are 3 repositories under systolic-arrays topic.

trevorpogue / algebraic-nnhw
AI acceleration using matrix multiplication with half the multiplications
hardware-acceleration machine-learning systolic-arrays artificial-intelligence deep-neural-networks computer-architecture hardware accelerator
Language:Python 253
UCLA-VAST / AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
automatic-generation fpga polyhedral-model systolic-arrays
Language:C++ 186
transfomers-silicon-research
aliemo / transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
accelerator bert fpga-accelerator gpu-acceleration hardware-designs pretrained-models processing-in-memory research-paper systolic-arrays transformer video-transformer fpga natural-language-processing vision-transformer
Language:Jupyter Notebook 158
diwu1990 / uSystolic-Sim
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
simulation systolic-arrays unary-computing stochastic-computing temporal-computing rate-coding temporal-coding
Language:C++ 56
rejunity / tiny-asic-1_58bit-matrix-mul
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
asic llm-inference systolic-arrays tinytapeout
Language:Verilog 39
horizon-research / systolic-array-dataflow-optimizer
A general framework for optimizing DNN dataflow on systolic array
dnn dataflow deconvolution systolic-arrays
Language:Python 29
IntelLabs / t2sp
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
dsl language compiler fpga gpu productivity portability performance systolic-arrays
Language:C++ 29
maao666 / HPDLA
Systolic-array based Deep Learning Accelerator generator
dla chisel3 systolic-arrays
Language:Verilog 23
ic-lab-duth / FusedGCN4HLS
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
graph-convolutional-networks machine-learning systolic-arrays three-matrix-multiplication high-level-synthesis
Language:C++ 20
Systolic-Array-for-Smith-Waterman
jasonlin316 / Systolic-Array-for-Smith-Waterman
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
smith-waterman local sequence-alignment systolic-arrays dynamic-programming verilog short-read
Language:Verilog 19
AIC2021 / AIC2021_TPU_Template
Template for project1 TPU
accelerator matrix-multiplication systolic-arrays tpu
Language:Verilog 11
alex-mckenna / clash-systolic
Systolic Networks in Clash
fpga haskell systolic-arrays
Language:Haskell 6
KevinWang96 / EE599_YihaoWang_7410178057
EE599 Accelerated Computing on FPGA
fpga verilog vivado odd-even-sort matrix-multiplication systolic-arrays barrel-shifter
Language:Verilog 6
gultai4ukr / PySAGS
Systolic arrays graphical simulator (SAGS), written in Python.
python systolic-arrays simulation modelling gui tkinter
Language:Python 5
YuFengUofR / dataflow_optimizer
A general framework for optimizing DNN dataflow on systolic array
systolic-arrays deconvolution simulation dnn dataflow dataflow-analysis
Language:Python 5
anthonyarusso / systolic-array
SystemVerilog module for matrix multiplication
pynq systemverilog systolic-arrays verilog
Language:SystemVerilog 3
joulook / Parallel-Processing-Spring-2021
In this repository you can find all of my projects for Parallel Processing Course when I was in 2nd semester of my master's at SUT.
cuda gpu-programming map-reduce multicore-programming multithreading openmp parallel-algorithms parallel-computing parallel-processing systolic-arrays jacobi-iteration parallel-quick-sort parallel-convex-hull parallel-jacobi parallel-matrix-multiplication
Language:Java 3
RayWright27 / SystemC-CNN-test-model
This is an unfinished test model of CNN, based on cnn.h5 Keras pretrained model EN10/KerasMNIST@4ef71d6/cnn.h5 .
cnn keras kernel systemc systolic-arrays
Language:Jupyter Notebook 1
dsa-shua / FPGA-SystolicArray
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
accelerator fpga hardware hardware-acceleration hardware-designs hdl matrix matrix-multiplication project pynq-z2 sdk systemverilog systolic-arrays verilog vitis vivado xilinx zynq-7000
Language:SystemVerilog 0
EMITLabGit / PsuedoSim
Analytical modeling tool for CNNs running on array-based accelerators.
accelerator cnn hardware integrated-circuit systolic-arrays
Language:Python 0
NeuroFan / SystolicArray
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
energy matlab simulation spice systolic systolic-arrays voltage
Language:SourcePawn
Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
chip-design logic-design sva systemverilog verification verilog systolic-arrays functional-coverage matrix-multiplication questasim amba-apb
Language:Verilog
sebyss / Visual-representation-of-systolic-arrays
Visual representation of how systolic arrays made in Unity3d. (Just code)
csharp unity3d systolic-arrays
Language:C#

systolic-arrays

trevorpogue / algebraic-nnhw

UCLA-VAST / AutoSA

aliemo / transfomers-silicon-research

diwu1990 / uSystolic-Sim

rejunity / tiny-asic-1_58bit-matrix-mul

horizon-research / systolic-array-dataflow-optimizer

IntelLabs / t2sp

maao666 / HPDLA

ic-lab-duth / FusedGCN4HLS

jasonlin316 / Systolic-Array-for-Smith-Waterman

AIC2021 / AIC2021_TPU_Template

alex-mckenna / clash-systolic

KevinWang96 / EE599_YihaoWang_7410178057

gultai4ukr / PySAGS

YuFengUofR / dataflow_optimizer

anthonyarusso / systolic-array

joulook / Parallel-Processing-Spring-2021

RayWright27 / SystemC-CNN-test-model

dsa-shua / FPGA-SystolicArray

EMITLabGit / PsuedoSim

NeuroFan / SystolicArray

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

sebyss / Visual-representation-of-systolic-arrays